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POWER DRIVER FOR STEPPER MOTORS INTEGRATED CIRCUITS
TRINAMIC Motion Control GmbH & Co. KG Hamburg, Germany
TMC2208/2 & TMC2224/0/5 family Datasheet
FEATURES AND BENEFITS
2 - phase stepper motors up to 2A coil current (peak) STEP/DIR Interface with 2, 4, 8, 16 or 32 microstep pin setting Smooth Running 256 microsteps by microPlyer™ interpolation stealthChop2™ silent motor operation spreadCycle™ highly dynamic motor control chopper Low RDSon LS 280mΩ & HS 290mΩ (typ. at 25°C) Voltage Range 4.75… 36V DC Automatic Standby current reduction (option) Internal Sense Resistor option (no sense resistors required) Passive Braking and Freewheeling Single Wire UART & OTP for advanced configuration options Integrated Pulse Generator for standalone motion Full Protection & Diagnostics Choice of QFN, TQFP and HTSSOP packages for best fit
APPLICATIONS
Compatible Design Upgrade 3D Printers Printers, POS Office and home automation Textile, Sewing Machines CCTV, Security ATM, Cash recycler HVAC
DESCRIPTION
The TMC2202, TMC2208, TMC2220, TMC and TMC2225 are ultra-silent motor driver ICs for two phase stepper motors. Their pinning is compatible to a number of legacy drivers. TRINAMICs sophisticated stealthChop 2 chopper ensures noiseless operation, maximum efficiency and best motor torque. Its fast current regulation and optional combination with spreadCycle allow for highly dynamic motion. Integrated power-MOSFETs handle motor current up to 1.4A RMS. Protection and diagnostic features support robust and reliable operation. A simple to use UART interface opens up more tuning and control options. Application specific tuning can be stored to OTP memory. Industries’ most advanced STEP/DIR stepper motor driver family upgrades designs to noiseless and most precise operation for cost- effective and highly competitive solutions.
TMC2202, TMC2208, TMC2220, TMC2224, TMC2225 Step/Dir Drivers for Two-Phase Bipolar Stepper Motors up to 2A peak - stealthChop™ for Quiet Movement - UART Interface Option.
BLOCK DIAGRAM
spreadCycle stealthChop
DRIVER
TMC220X
TMC222X
256 μStep Sequencer
Pulse Generator
UART optional control
Power Supply
Motor
Step/Dir
Step Multiplyer
spreadCycle stealthChop
DAC Reference
IREF optional current scaling
UART Control
CLK
Control Register Set
Standstill CurrentReduction
CLK Oscillator / Selector
Charge Pump
+5V Regulator
Mode Selection
Configuration Pins
OTP memory
Protection & Diagnostics
Diag Out / Index
APPLICATION EXAMPLES: SIMPLE SOLUTIONS – HIGHLY EFFECTIVE
The TMC22xx family scores with power density, integrated power MOSFETs, smooth and quiet operation, and a congenial simplicity. The TMC22xx covers a wide spectrum of applications from battery systems to embedded applications with up to 2A motor current per coil. TRINAMICs unique chopper modes spreadCycle and stealthChop2 optimize drive performance. stealthChop reduces motor noise to the point of silence at low velocities. Standby current reduction keeps costs for power dissipation and cooling down. Extensive support enables rapid design cycles and fast time-to-market with competitive products.
STANDALONE REPLACEMENT FOR LEGACY STEPPER DRIVER
S/D (^) N S
0A+
0A- 0B+
TMC22xx
0B-
ERROR, INDEX
S/D (^) N S
0A+
0A- 0B+
TMC22xx
0B-
High-LevelInterface CPU UART
UART INTERFACE FOR FULL DIAGNOSTICS AND CONTROL
Sense Resistors may be omitted
TMC2208-EVAL EVALUATION BOARD
ORDER CODES
Order code Description Size [mm^2 ] TMC2208-LA stealthChop standalone driver; QFN28 (RoHS compliant) 5 x 5 TMC2224-LA stealthChop standalone driver; QFN28 (RoHS compliant) 5 x 5 TMC2202-WA stealthChop driver; wettable edge QFN32 (RoHS compliant) 5 x 5 TMC2220-TA Option package: TQFP 48 – please request for availability! 9 x 9 TMC2225-SA Option package: HTSSOP28 – please request for availability! 9.7 x 6. TMC2208-EVAL Evaluation board for TMC2208 stepper motor driver 85 x 55 TMC2224-EVAL Evaluation board for TMC22 24 stepper motor driver 85 x 55 TMC 22 xx-Bridge Connector and jumper board fitting to TMC22xx family 61 x 38 STARTRAMPE Baseboard for TMC2208-EVAL and further evaluation boards 85 x 55
In this example, configuration is hard wired via pins. Software based motion control generates STEP and DIR (direction) signals, INDEX and ERROR signals report back status information.
A CPU operates the driver via step and direction signals. It accesses diagnostic information and configures the TMC22xx via the UART interface. The CPU manages motion control and the TMC22xx drives the motor and smoo- thens and optimizes drive performance.
The TMC22xx-EVAL is part of TRINAMICs universal evaluation board system which provides a convenient handling of the hardware as well as a user-friendly software tool for evaluation. The TMC22xx evaluation board system consists of three parts: STARTRAMPE (base board), TMC2208- BRIDGE (connector board with several test points and stand-alone settings), and TMC22xx-EVAL.
1 Principles of Operation The TMC22xx family of stepper drivers is intended as a drop-in upgrade for existing low cost stepper driver applications. Its silent drive technology stealthChop enables non-bugging motion control for home and office applications. A highly efficient power stage enables high current from a tiny package. The TMC22xx requires just a few control pins on its tiny package. They allow selection of the most important setting: the desired microstep resolution. A choice of 2, 4, 8, 16 or 32 microsteps adapts the driver to the capabilities of the motion controller. Some package options also allow chopper mode selection by pin. Even at low microstepping rate, the TMC22xx offers a number of unique enhancements over comparable products: TRINAMICs sophisticated stealthChop2 chopper plus the microstep enhancement microPlyer ensure noiseless operation, maximum efficiency and best motor torque. Its fast current regulation and optional combination with spreadCycle allow for highly dynamic motion. Protection and diagnostic features support robust and reliable operation. A simple-to-use 8 bit UART interface opens up more tuning and control options. Application specific tuning can be stored to on-chip OTP memory. Industries’ most advanced step & direction stepper motor driver family upgrades designs to noiseless and most precise operation for cost-effective and highly competitive solutions.
22n50V 100n16V
ENN GND DIE PAD
microPlyer
Full Bridge A
Full Bridge B
+VM VS
stepper motor
N S
OA OA
OB OB
Driver
100n
BRB
100μF
CPO CPI
BRA RSA
Use low inductivity SMDtype, e.g. 1206, 0.5W for RSA and RSB
RSB
100n
VREF VCP
opt. driver enable
stealthChop
spreadCycle
256 MicrostepSequencer IntegratedRsense^ IREF
Stand StillCurrent Reduction
2.2μ6.3V 5VOUT
Analog currentscaling or leaveopen
Low ESR type
short path to die pad^ Place near IC with
Connect directlyto GND plane
VCC_IO Connect directlyto GND plane
TMC22xx Step&Dir input 5V Voltageregulator charge pump
opt. ext. clock CLK_IN 10-16MHz 3.3V or 5V I/O voltage (^) 100n
Analog Scaling VREF
ProgrammableDiagnostic Outputs
Configuration Interface
MS MS SPREAD
INDEX
DIAG
Configuration (GND or VCC_IO)
Index pulse
Driver error
PDN/UART (^) TRINAMIC 2016B. Dwersteg, ©
Trimmed CLK oscillator/selector
- Register BlockUART interface
ConfigurationMemory (OTP)
(not with TMC2202)
(only TMC222x) optional UART interface
IREF Step PulseGenerator
STEP Step and Directionmotion control DIR
Figure 1.1 TMC22xx basic application block diagram
THREE MODES OF OPERATION:
OPTION 1: Standalone STEP/DIR Driver (Legacy Mode)
A CPU (μC) generates step & direction signals synchronized to additional motors and other components within the system. The TMC22xx operates the motor as commanded by the configuration pins and STEP/DIR signals. Motor run current either is fixed, or set by the CPU using the analog input VREF. The pin PDN_UART selects automatic standstill current reduction. Feedback from the driver to the CPU is granted by the INDEX and DIAG output signals. Enable or disable the motor using the ENN pin.
OPTION 2: Standalone STEP/DIR Driver with OTP pre-configuration
Additional options enabled by pre-programming OTP memory (label UART & OTP):
- Tuning of the chopper to the application for application tailored performance
- Cost reduction by switching the driver to internal sense resistor mode
- Adapting the automatic power down level and timing for best application efficiency
S/D (^) N S
0A+
0A- 0B+
TMC22xx
0B-
High-LevelInterface CPU ERROR, INDEX
TXD only or bit bang UART Other drivers (^) External pre- programming
Figure 1.2 Stand-alone driver with pre-configuration
To enable the additional options, either one-time program the driver’s OTP memory, or store configuration in the CPU and transfer it to the on-chip registers following each power-up. Operation uses the same signals as Option 1. Programming does not need to be done within the application - it can be executed during testing of the PCB! Alternatively, use bit-banging by CPU firmware to configure the driver. Multiple drivers can be programmed at the same time using a single TXD line.
OPTION 3: STEP/DIR Driver with Full Diagnostics and Control
Similar to Option 2, but pin PDN_UART is connected to the CPU UART interface.
Additional options (label UART):
- Detailed diagnostics and thermal management
- Passive braking and freewheeling for flexible, lowest power stop modes
- More options for microstep resolution setting (fullstep to 256 microstep)
- Software controlled motor current setting and more chopper options
This mode allows replacing all control lines like ENN, DIAG, INDEX, MS1, MS2, and analog current setting VREF by a single interface line. This way, only three signals are required for full control: STEP, DIR and PDN_UART. Even motion without external STEP pulses is provided by an internal programmable step pulse generator: Just set the desired motor velocity. However, no ramping is provided by the TMC22xx. Access to multiple driver ICs is possible using an analog multiplexer IC.
1.1 Key Concepts
The TMC22xx implements advanced features which are exclusive to TRINAMIC products. These features contribute toward greater precision, greater energy efficiency, higher reliability, smoother motion, and cooler operation in many stepper motor applications.
stealthChop2 ™ No-noise, high-precision chopper algorithm for inaudible motion and inaudible standstill of the motor. Allows faster motor acceleration and deceleration than stealthChop™ and extends stealthChop to low stand still motor currents.
spreadCycle ™ High-precision cycle-by-cycle current control algorithm for highest dynamic movements.
microPlyer™ Microstep interpolator for obtaining full 256 microstep smoothness with lower resolution step inputs starting from fullstep
In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage conditions for enhancing safety and recovery from equipment malfunctions.
UART
UART OTP
For highest velocity applications, spreadCycle is an option to stealthChop2. It can be enabled via input pin (TMC222x) or via UART and OTP. stealthChop2 and spreadCycle may even be used in a combined configuration for the best of both worlds: stealthChop2 for no-noise stand still, silent and smooth performance, spreadCycle at higher velocity for high dynamics and highest peak velocity at low vibration.
spreadCycle is an advanced cycle-by-cycle chopper mode. It offers smooth operation and good resonance dampening over a wide range of speed and load. The spreadCycle chopper scheme automatically integrates and tunes fast decay cycles to guarantee smooth zero crossing performance.
Benefits of using stealthChop2:
- Significantly improved microstepping with low cost motors
- Motor runs smooth and quiet
- Absolutely no standby noise
- Reduced mechanical resonance yields improved torque
1.5 Precise clock generator and CLK input
The TMC22xx provides a factory trimmed internal clock generator for precise chopper frequency and performance. However, an optional external clock input is available for cases, where quartz precision is desired, or where a lower or higher frequency is required. For safety, the clock input features timeout detection, and switches back to internal clock upon fail of the external source.
1.6 Automatic Standstill Power Down
An automatic current reduction drastically reduces application power dissipation and cooling requirements. Per default, the stand still current reduction is enabled by pulling PDN_UART input to GND. It reduces standstill power dissipation to less than 33% by going to slightly more than half of the run current. Modify stand still current, delay time and decay via UART, or pre-programmed via internal OTP. Automatic freewheeling and passive motor braking are provided as an option for stand still. Passive braking reduces motor standstill power consumption to zero, while still providing effective dampening and braking!
t
CURRENT
TPOWERDOWN power down RMS motor current trace with pin PDN=0 delay time
IHOLD
IRUN
IHOLDDELAY power down ramp time
STEP
Figure 1.3 Automatic Motor Current Power Down
1.7 Index Output
The index output gives one pulse per electrical rotation, i.e. one pulse per each four fullsteps. It shows the internal sequencer microstep 0 position ( MSTEP near 0). This is the power on position. In combination with a mechanical home switch, a more precise homing is enabled.
2 Pin Assignments
The TMC22xx family comes in a number of package variants in order to fit different footprints. Please check for availability.
2.1 Package Outline TMC
OB
ENN
GND
CPO
OB1 BRA
CLK
INDEX
MS2DIAG
STEP
VREF
GND
DIR
OA
CPI
VCP
PDN_UART
MS
5VOUT
VSBRB - OA1 VS
VCC_IO
(^1) (^2) (^3) (^4) (^5) (^6)
7
21 20 19 18 17 16 15
28 27 26 25 24 23 22
8 9 10 11 12 13 14
TMC
QFN
Pad=GND
© B. Dwersteg, TRINAMIC
Figure 2.1 TMC2208 Pinning Top View – type: QFN28, 5x5mm², 0.5mm pitch
2.2 Signal Descriptions TMC
Pin Number Type Function
OB2 1 Motor coil B output 2
ENN 2 DI Enable not input. The power stage becomes switched off (all motor outputs floating) when this pin becomes driven to a high level. GND 3, 18 GND. Connect to GND plane near pin. CPO 4 Charge pump capacitor output. CPI 5 Charge pump capacitor input. Tie to CPO using 22nF 50V capacitor. VCP 6 Charge pump voltage. Tie to VS using 100nF capacitor.
N.C.
Unused pin, leave open or connect to GND for compatibility to future versions.
5VOUT 8
Output of internal 5V regulator. Attach 2.2μF to 4.7μF ceramic capacitor to GND near to pin for best performance. Provide the shortest possible loop to the GND pad. MS1 9 DI (pd) Microstep resolution configuration (internal pull down resistors) MS2 10 DI (pd)^ MS2, MS1: 00: 1/8, 01: 1/2, 10: 1/4 11: 1/ DIAG 11 DO Diagnostic output. Hi level upon driver error. Reset by ENN=high. INDEX 12 DO Configurable index output. Provides index pulse.
CLK 13 DI CLK input. Tie to GND using short wire for internal clock or supply external clock.
PDN_UART 14 DIO
Power down not control input (low = automatic standstill current reduction). Optional UART Input/Output. Power down function can be disabled in UART mode. VCC_IO 15 3.3V to 5V IO supply voltage for all digital pins.
Pin Number Type Function
GND 6, 19 GND. Connect to GND plane near pin. CPO 7 Charge pump capacitor output. CPI 8 Charge pump capacitor input. Tie to CPO using 22nF 50V capacitor. VCP 9 Charge pump voltage. Tie to VS using 100nF capacitor.
5VOUT 10
Output of internal 5V regulator. Attach 2.2μF to 4.7μF ceramic capacitor to GND near to pin for best performance. Provide the shortest possible loop to the GND pad. MS1 11 DI (pd) Microstep resolution configuration (internal pull down resistors) MS2 12 DI (pd) MS2, MS1: 00: 1/8, 01: 1/2, 10: 1/4 11: 1/ DIAG 13 DO Diagnostic output. Hi level upon driver error. Reset by ENN=high.
CLK 14 DI CLK input. Tie to GND using short wire for internal clock or supply external clock.
PDN_UART 15 DIO
Power down not control input (low = automatic standstill current reduction). Optional UART Input/Output. Power down function can be disabled in UART mode. VCC_IO 16 3.3V to 5V IO supply voltage for all digital pins. STEP 17 DI STEP input
VREF 18 AI Analog reference voltage for current scaling or reference current for use of internal sense resistors (optional mode) DIR 20 DI (pd) DIR input (internal pull down resistor) OA2 24 Motor coil A output 2
BRA 25 Sense resistor connection for coil A. Place sense resistor to GND near pin. Tie to GND when using internal sense resistor. OA1 27 Motor coil A output 1 OB1 30 Motor coil B output 1
BRB 32 Sense resistor connection for coil B. Place sense resistor to GND near pin. Tie to GND when using internal sense resistor.
Exposed die pad
Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane. Serves as GND pin for power drivers and analogue circuitry.
2.5 Package Outline TMC
MS
INDEX
GND
CPO
VS
- DIR
OA1OB1BRBOB
TEST
GND
5VOUT
VCC_IO
PDN_UART
DIAG
CPI
VCP
VS
OA2BRA
MS1CLK STEPENN SPREAD
VREF
(^1) (^2) (^3) (^4) (^5) (^6)
7
21 20 19 18 17 16 15
28 27 26 25 24 23 22
8 9 10 11 12 13 14
TMC
QFN
Pad=GND
© B. Dwersteg, TRINAMIC
Figure 2.3 TMC2224 Pinning Top View – type: QFN28, 5x5mm², 0.5mm pitch
2.6 Signal Descriptions TMC
Pin Number Type Function
MS1 28 DI (pd) Microstep resolution configuration (internal pull down resistors) MS2 1 DI (pd) MS2, MS1: 00: 1/4, 01: 1/8, 10: 1/16, 11: 1/ INDEX 2 DO Configurable index output. Provides index pulse. GND 3, 17 GND. Connect to GND plane near pin. CPO 4 Charge pump capacitor output. CPI 5 Charge pump capacitor input. Tie to CPO using 22nF 50V capacitor. VCP 6 Charge pump voltage. Tie to VS using 100nF capacitor.
VS 7, 14 Motor supply voltage. Provide filtering capacity near pin with shortest possible loop to GND pad. OA2 8 Motor coil A output 2
BRA 9 Sense resistor connection for coil A. Place sense resistor to GND near pin. Tie to GND when using internal sense resistor. OA1 10 Motor coil A output 1 OB1 11 Motor coil B output 1
BRB 12 Sense resistor connection for coil B. Place sense resistor to GND near pin. Tie to GND when using internal sense resistor. OB2 13 Motor coil B output 2
VREF 15 AI Analog reference voltage for current scaling or reference current for use of internal sense resistors (optional mode) TEST 16 Connect to GND. May alternatively be left open or connected to VREF.
5VOUT 18
Output of internal 5V regulator. Attach 2.2μF to 4.7μF ceramic capacitor to GND near to pin for best performance. Provide the shortest possible loop to the GND pad. VCC_IO 19 3.3V to 5V IO supply voltage for all digital pins.
PDN_UART 20
DIO
(pd)
Power down not control input (low = automatic standstill current reduction). (internal pull down resistor) Optional UART Input/Output. Power down function can be disabled in UART mode. DIAG 21 DO Diagnostic output. Hi level upon driver error. Reset by ENN=high. SPREAD 22 DI (pd) Chopper mode selection: Low=stealthChop, High=spreadCycle DIR 23 DI (pd) DIR input (internal pull down resistor)
ENN 24 DI Enable not input. The power stage becomes switched off (all motor outputs floating) when this pin becomes driven to a high level. STEP 25 DI (pd) STEP input (internal pull down resistor)
N.C. 26 Unused pin, leave open or connect to GND for compatibility to future versions.
CLK 27 DI CLK input. Tie to GND using short wire for internal clock or supply external clock.
Exposed die pad
Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane. Serves as GND pin for power drivers and analogue circuitry.
Pin Number Type Function
STEP 22 DI (pd) STEP input (internal pull down resistor)
N.C. 23 Unused pin, leave open or connect to GND for compatibility to future versions.
CLK 24 DI CLK input. Tie to GND using short wire for internal clock or supply external clock. MS1 25 DI (pd) Microstep resolution configuration (internal pull down resistors) MS2 26 DI (pd)^ MS2, MS1: 00: 1/4, 01: 1/8, 10: 1/16, 11: 1/ INDEX 27 DO Configurable index output. Provides index pulse.
Exposed die pad
Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane. Serves as GND pin for power drivers and analogue circuitry.
2.9 Package Outline TMC
25
26
37
24
CPO
OA
- OB2OB2- - OA2OA2 BRA
TEST
OB
SPREAD
5VIN
DIR STEP
VCC_IO
OB1^1
GND
VCC_IO
VS
VS
GND
VREF
CPI
VS
OA
PDN_UART
ENN
5VOUT
2 3 4 5 6 7 8 9
10 11
14 15 16 17 18 19 20 21 22 23
36 35 34 33 32 31 30 29 28 27
48 47 46 45 44 43 42 41 40 39
38
GND
13
BRA
VS
Pad = GND DIAG^12
INDEX
CLKMS
MS
VCP
BRBBRB
TMC2220-TA
TQFP-
9mm x 9mm
Figure 2.5 TMC2220 Pinning Top View – type: TQFP-EP 48, 9x9mm² over pins, 0.5mm pitch
2.10 Signal Descriptions TMC
Pin Number Type Function
OB1 1, 2 Motor coil B output 1
VS
Motor supply voltage. Provide filtering capacity near pin with shortest possible loop to GND pad. TEST 8 Connect to GND. May alternatively be left open.
GND
GND. Connect to GND plane near pin.
VCC_IO 10, 24 3.3V to 5V IO supply voltage for all digital pins.
Pin Number Type Function
PDN_UART 11
DIO
(pd)
Power down not control input (low = automatic standstill current reduction). (internal pull down resistor) Optional UART Input/Output. Power down function can be disabled in UART mode.
5 VOUT 15
Output of internal 5V regulator. Attach 2.2μF to 4.7μF ceramic capacitor to GND near to pin for best performance. Provide the shortest possible loop to the GND pad. 5VIN 16 Input of 5V supply. Directly connect to 5VOUT terminal. DIAG 12 DO Diagnostic output. Hi level upon driver error. Reset by ENN=high. SPREAD 17 DI (pd) Chopper mode selection: Low=stealthChop, High=spreadCycle DIR 18 DI (pd) DIR input (internal pull down resistor)
ENN 19 DI Enable not input. The power stage becomes switched off (all motor outputs floating) when this pin becomes driven to a high level. STEP 20 DI (pd) STEP input (internal pull down resistor) INDEX 21 DO Configurable index output. Provides index pulse.
CLK 22 DI CLK input. Tie to GND using short wire for internal clock or supply external clock. MS1 23 DI (pd) Microstep resolution configuration (internal pull down resistors) MS2 25 DI (pd)^ MS2, MS1: 00: 1/4, 01: 1/8, 10: 1/16, 11: 1/
VREF 26 AI Analog reference voltage for current scaling or reference current for use of internal sense resistors (optional mode) CPO 28 Charge pump capacitor output. CPI 30 Charge pump capacitor input. Tie to CPO using 22nF 50V capacitor. VCP 31 Charge pump voltage. Tie to VS using 100nF capacitor. OA1 35, 36 Motor coil A output 1
BRA 37, 38 Sense resistor connection for coil A. Place sense resistor to GND near pin. Tie to GND when using internal sense resistor. OA2 40, 41 Motor coil A output 2 OB2 44, 45 Motor coil B output 2
BRB 47, 48 Sense resistor connection for coil B. Place sense resistor to GND near pin. Tie to GND when using internal sense resistor.
N.C. Unused pin, leave open or connect to GND for compatibility to future versions.
Exposed die pad
Connect the exposed die pad to a GND plane. Provide as many as possible vias for heat transfer to GND plane. Serves as GND pin for power drivers and analogue circuitry.
VCC_IO
TMC22xx Step&Dir input 5V Voltageregulator charge pump
22n50V 100n16V
CLK_IN
ENN GND DIE PAD
opt. ext. clock 10-16MHz 3.3V or 5V I/O voltage (^) 100n
microPlyer
Full Bridge A
Full Bridge B
+VM VS
stepper motor S^ N
OA OA
OB OB
Driver
100n
BRB
100μF
CPO CPI
BRA
100n
VCP
Analog Scaling
VREF
VREF
opt. driver enable
Programmable Diagnostic Outputs
ConfigurationInterface
MS MS SPREAD
INDEX
DIAG
Configuration (GND/open or VCC_IO)
Index pulse
Driver error
PDN/UART (^) TRINAMIC 2016B. Dwersteg, ©
CLK oscillator/^ Trimmed selector
UART interface
Configuration Memory (OTP)
(not with TMC2202)
(only TMC222x)
stealthChop
spreadCycle
Integrated Rsense
IREF
256 Microstep IREF Sequencer
Step Pulse Generator Stand StillCurrent Reduction
STEP DIR
2.2μ6.3V 5VOUT
Step and Direction motion control
RREF
Attention Start with ENN=high!: Set GCONF.1 or OTP0.6prior to enabling the driver!
Low ESR type
Connect directlyto GND plane
Connect directlyto GND plane
short path to die padPlace near IC with
optional UART interface
Figure 3.2 Application circuit using RDSon based sensing
3.3 5V Only Supply
22n50V 100n16V
ENN GND DIE PAD
microPlyer
Full Bridge A
Full Bridge B
4.7-5.4V VS
stepper motor S^ N
OA OA
OB OB
Driver
100n
BRB
100μF
CPO CPI
BRA RSA
RSB
100n
VREF VCP
opt. driver enable
stealthChop
spreadCycle
256 MicrostepSequencer IntegratedRsense^ IREF
Stand Still ReductionCurrent
6.3V^ 10μ 5VOUT
10R
Use low inductivity SMDtype, e.g. 1206, 0.5W for RSA and RSB
Low ESR type
short path to die pad^ Place near IC with
Connect directlyto GND plane
VCC_IO Connect directlyto GND plane
TMC22xx Step&Dir input 5V Voltageregulator charge pump
opt. ext. clock CLK_IN 10-16MHz 3.3V or 5V I/O voltage (^) 100n
Analog Scaling VREF
ProgrammableDiagnostic Outputs
ConfigurationInterface
MS MS SPREAD
INDEX
DIAG
Configuration (GND/open or VCC_IO)
Index pulse
Driver error
PDN/UART (^) TRINAMIC 2016B. Dwersteg, ©
Trimmed CLK oscillator/selector
UART interface
Configuration Memory (OTP)
(not with TMC2202)
(only TMC222x)
IREF Step Pulse Generator
STEP Step and Directionmotion control DIR
Optionalinternal 5V reference – bridges the
optional UART interface
Figure 3.3 5V only operation
While the standard application circuit is limited to roughly 5.2 V lower supply voltage, a 5 V only application lets the IC run from a 5 V +/-5% supply. In this application, linear regulator drop must be
minimized. Therefore, the internal 5V regulator is filtered with a higher capacitance. An optional resistor bridges the internal 5V regulator by connecting 5VOUT to the external power supply. This RC filter keeps chopper ripple away from 5VOUT. With this resistor, the external supply is the reference for the absolute motor current and must not exceed 5.5V.
3.4 Configuration Pins
The TMC22xx family members provide three or four configuration pins depending on the package option. These pins allow quick configuration for standalone operation. Several additional options can be set by OTP programming. In UART mode, the configuration pins can be disabled in order to set a different configuration via registers.
PDN_UART: CONFIGURATION OF STANDSTILL POWER DOWN
PDN_UART Current Setting GND Enable automatic power down in standstill periods VCC_IO Disable UART interface When using the UART interface, the configuration pin should be disabled via GCONF.pdn_disable = 1. Program IHOLD as desired for standstill periods.
OPTIONS FOR TMC220X DEVICES, ONLY:
MS1/MS2: CONFIGURATION OF MICROSTEP RESOLUTION FOR STEP INPUT (TMC220X)
MS2 MS 1 Microstep Setting GND GND 8 microsteps GND VCC_IO 2 microsteps (half step) VCC_IO GND 4 microsteps (quarter step) VCC_IO VCC_IO 16 microsteps
OPTIONS FOR TMC222X DEVICES, ONLY:
SPREAD (ONLY WITH TMC222X): SELECTION OF CHOPPER MODE
SPREAD Chopper Setting GND or Pin open / not available
stealthChop is selected. Automatic switching to spreadCycle in dependence of the step frequency can be programmed via OTP.
VCC_IO spreadCycle operation.
MS1/MS2: CONFIGURATION OF MICROSTEP RESOLUTION FOR STEP INPUT (TMC222X)
MS2 MS1 Microstep Setting GND GND 4 microsteps (quarter step) GND VCC_IO 8 microsteps VCC_IO GND 16 microsteps VCC_IO VCC_IO 32 microsteps
3.5 High Motor Current
When operating at a high motor current, the driver power dissipation due to MOSFET switch on- resistance significantly heats up the driver. This power dissipation will significantly heat up the PCB cooling infrastructure, if operated at an increased duty cycle. This in turn leads to a further increase of driver temperature. An increase of temperature by about 100°C increases MOSFET resistance by roughly 50%. This is a typical behavior of MOSFET switches. Therefore, under high duty cycle, high load conditions, thermal characteristics have to be carefully taken into account, especially when increased environment temperatures are to be supported. Refer the thermal characteristics and the layout hints for more information. As a thumb rule, thermal properties of the PCB design become
4 UART Single Wire Interface
The UART single wire interface allows control of the TMC22xx with any microcontroller UART. It shares transmit and receive line like an RS485 based interface. Data transmission is secured using a cyclic redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can be bridged without danger of wrong or missed commands even in the event of electro-magnetic disturbance. The automatic baud rate detection makes this interface easy to use.
4.1 Datagram Structure
4.1.1 Write Access
UART WRITE ACCESS DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first 0 … 63 sync + reserved 8 bit slave address
RW + 7 bit register addr. 32 bit data CRC 0…7 8…15 16…23 24…55 56… 1 0 1 0 Reserved (don’t cares but included in CRC) SLAVEADDR =0 register address 1 data bytes 3, 2, 1, 0 (high to low byte) CRC
0 1 2 3 4 5 6 7 8 … 15 16 … 23 24 … 55 56 … 63
A sync nibble precedes each transmission to and from the TMC22xx and is embedded into the first transmitted byte, followed by an addressing byte (0 for TMC22xx). Each transmission allows a synchronization of the internal baud rate divider to the master clock. The actual baud rate is adapted and variations of the internal clock frequency are compensated. Thus, the baud rate can be freely chosen within the valid range. Each transmitted byte starts with a start bit (logic 0, low level on SWIOP) and ends with a stop bit (logic 1, high level on SWIOP). The bit time is calculated by measuring the time from the beginning of start bit (1 to 0 transition) to the end of the sync frame ( to 0 transition from bit 2 to bit 3). All data is transmitted bytewise. The 32 bit data words are transmitted with the highest byte first.
A minimum baud rate of 9000 baud is permissible, assuming 20 MHz clock (worst case for low baud rate). Maximum baud rate is fCLK/16 due to the required stability of the baud clock.
The slave address SLAVEADDR is always 0 for the TMC22xx.
The communication becomes reset if a pause time of longer than 63 bit times between the start bits of two successive bytes occurs. This timing is based on the last correctly received datagram. In this case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of bus idle time. This scheme allows the master to reset communication in case of transmission errors. Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treated the same way. This allows a safe re-synchronization of the transmission after any error conditions. Remark, that due to this mechanism an abrupt reduction of the baud rate to less than 15 percent of the previous value is not possible.
Each accepted write datagram becomes acknowledged by the receiver by incrementing an internal cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the success of an initialization sequence or single write accesses. Read accesses do not modify the counter.
UART
The UART line must be logic high during idle state. Therefore, the power down function cannot be assigned by the pin PDN_UART in between of transmissions. In an application using the UART interface, set the desired power down function by register access and set pdn_disable in GCONF to disable the pin function.
4.1.2 Read Access
UART READ ACCESS REQUEST DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
sync + reserved 8 bit slave address RW + 7 bit register address CRC 0...7 8…15 16…23 24… 1 0 1 0 Reserved (don’t cares but included in CRC) SLAVEADDR =0 register address 0 CRC
0 1 2 3 4 5 6 7 8 … 15 16 … 23 24 … 31
The read access request datagram structure is identical to the write access datagram structure, but uses a lower number of user bits. Its function is the addressing of the slave and the transmission of the desired register address for the read access. The TMC22xx responds with the same baud rate as the master uses for the read request.
In order to ensure a clean bus transition from the master to the slave, the TMC22xx does not immediately send the reply to a read access, but it uses a programmable delay time after which the first reply byte becomes sent following a read request. This delay time can be set in multiples of eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the master.
UART READ ACCESS REPLY DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first 0 ...... 63 sync + reserved 8 bit^ master address
RW + 7 bit register addr. 32 bit data CRC 0…7 8…15 16…23 24…55 56… 1 0 1 0 reserved (0) 0xFF register address 0 data bytes 3, 2, 1, 0 (high to low byte) CRC
0 1 2 3 4 5 6 7 8 … 15 16 … 23 24 … 55 56 … 63
The read response is sent to the master using address code %11111111. The transmitter becomes switched inactive four bit times after the last bit is sent.
Address %11111111 is reserved for read access replies going to the master.
