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Prof. Sakshum Jasveer delivered this lecture at Bhupendra Narayan Mandal University for Verilog and HDL course. Its main points are: Comments, Operators, Constants, Identifiers, Keywords, Tokens, Tasks, Functions, Macros, Data, Types
Typology: Slides
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Department of Electrical Engineering
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Department of Electrical Engineering
Pakistan Institute of Engineering and Applied Sciences
comment.
Department of Electrical Engineering
A logical operator interprets its operands as either true or false and always evaluate to a 1-bit true or false result. A bitwise operator interprets its operands as vectors and returns a vector. Verilog supports the following logical operators
Negation
(takes
operand)
And
(takes
operands)
Or
(takes
operands)
If the operand supplied to a logical operand is equal to zero, it is interpreted as false. Any non-zero operand is interpreted as true. The logical operation is performed on the operand(s) and a 1-bit value is returned.
Department of Electrical Engineering
Pakistan Institute of Engineering and Applied Sciences
Verilog supports the following
bitwise operators
~^
-^
Negation
(takes
1
operand)
&^
-^
And
(takes
2
operands)
|^
-^
Or
(takes
2
operands)
^^
-^
Xor (takes
2
operands)
^~
Xnor
(takes
2
operands)
~^
Xnor
(takes
2
operands)
For a bitwise operator, the logical operation is performed on each bit position of the operand(s). If one operand is shorter than the other, it is bit extended with zeros in the left-most bits to match the length of the longer operand. The result returned is a vector of equal length to the longest operand. Examples: A^
=^
4'b B^
=^
6'b C^
=^
1'b A^
&&
B
=
1'b
A^
&^
B^
=^
6'b
A^
&&
C
=
1'b
A^
&^
C^
=^
4'b
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Pakistan Institute of Engineering and Applied Sciences
Constants
-^
Radix Specifiers The radix specifier indicates that the digits following are decimal ('d),hexidecimal ('h), octal ('o), or binary ('b). Each digit represents theappropriate number of bits for the radix.
-^
These are examples of integer constants:
^
123 ^
1'b ^
8'h ^
12'bx ^
16'd ^
3'b1xz ^
32'h8f_32_ab_f
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Pakistan Institute of Engineering and Applied Sciences
Constants – Padding and Truncation
-^
Padding and Truncation
:
The number of bits represented by the digits in the value part of the constant may be more or less than the given size. If there are more, then the high order bits are truncated. For example,
7'h8fis
equivalent to7'h0f
-^
If the size is greater than the number of bits in the valuepart (which is a much more common case), then thenumber is padded on the left (high order part) with 0.However, if the left-most digit in the value part is x or z,then the number is padded with x or z.
12'h3is
equivalent
to12'b
12'h3xis
equivalent to12'b00000011xxxx
12'bxis equivalent to12'bxxxxxxxxxxxx 12'oz37is equivalent to12'bzzzzzz
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Pakistan Institute of Engineering and Applied Sciences
Constant -> Real
-^
Real numbers are represented in IEEE standard 754-1985 doubleprecision format. Real constants can be written in decimal notationor scientific notation. If a decimal point is present in the number,there must be at least one digit on either side of it.
-^
When real numbers are converted to integers, they are rounded, nottruncated. Numbers which end in .5 are rounded away from zero.For example, 1.5 rounds to 2 and -1.5 rounds to -2.
-^
These are examples of real constants:^
^
^
^
1.2E ^
13.0e- ^
23e ^
123.111_222_333E-
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Pakistan Institute of Engineering and Applied Sciences
-^
Identifiers
name objects.
-^
Objects
which
can
be
named
are
modules,
instances,
nets,
registers,
parameters, tasks, functions, blocks, and source macro. Identifiers may bemade up of any number of letters, digits, and {_$}:
simple_identifier ::= [a-zA-Z_]{[a-zA-Z0-9_$]}
-^
That is, the first character must be alphabetic or "", and the rest may bealphabetic, numeric, "", or "$". Identifiers may be as long as 1 millioncharacters and are case-sensitive.
-^
Here are some examples of identifiers:
^
shiftreg_a ^
busa_index ^
error_condition ^
merge ^
_bus ^
n$
^
Identifiers can also be "hierarchical". That is, an identifier can be composedof more than one simple_identifier linked by periods:
abc.def top.foo.bar.xyz system.board.chip.wire
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A scope is a set of identifiers which must be unique. That is, all ofthe identifiers in the same scope must be different from each other,but they may be the same as identifiers in a different scope.
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Verilog defines several scopes in which identifiers are defined.^ 1. Module
Net names, top-level register names, task names, function names,module and primitive instance names, and port names exist in themodule's scope. That is, two different modules can each have a netnamed "net1 or a module instance named "foo_inst". However, therecan be only one "net1" or "foo_inst" in a single module.
Tasks, functions, and named blocks allow registers, parameters, andnamed blocks to be defined within them. These names exist inhierarchical name spaces. That is, an identifier in an outer scope(module, task, function, or block) may be redefined in an inner scope(task, function, or block).
There is a single scope which contains all module types (i.e. thename used in the module definition). Thus, there can be only onemodule of type "DF99".
Source macros have a single global scope that crosses moduleboundaries.
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-^
Verilog contains keywords, which are predefined, non-escaped identifiers.An escaped identifier is not treated as a keyword. For example, \begin isnot a keyword.
-^
These are the keywords in Verilog: always
inout
rtranif
and
input
rtranif
assign
integer
scalared
begin
join
small
buf
large
specify
bufif
macromodul
e
specparam
bufif
medium
strength
case
module
strong
casex
nand
strong
casez
negedge
supply
cmos
nmos
supply
deassign
nor
table
default
not
task
defparam
notif
time
disable
notif
tran
edge
or
tranif
else
output
tranif
end
parameter
tri
endcase
pmos
tri
endmodule
posedge
tri
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Source macros
are a special case of a general class of statements
called compiler directives. A Verilog source macro is very similar tothe
source
macro
facility
in
which
is
implemented
by
the
preprocessor. In Verilog, the source macro is defined by means of adefine statement. Notice that the first character is "
", the back-quote.
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An identifier is defined as a macro by associating a string of text tobe
substituted
whenever
the
macro
identifier
is
used.
Macro
identifiers are marked in the text by preceding them with the ""(back-quote again). For example,^
define
mymacro
this
is
some
text
... $display("`mymacro"); ... This
would
the
string
this
is
some
text
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Department of Electrical Engineering
Note that there is no trailing semi-colon in the macro definition. Ifthere was, it would be included in the macro text to be substituted. Itis
possible
to
have
a
macro
invocation
within
the
macro
text
definition.
-^
Macro definitions are global, and are text-order dependent. That is,the definition must appear before it is used, but the macro may beused in any module which appears in the source stream thereafter.It is possible to redefine a macro, and the new definition overridesthe old one for all subsequent uses.
-^
Macro definitions may appear anywhere in the source stream, bothwithin and outside of module definitions. A macro definition remainsin effect for the remainder of the source stream, or until the macro isredefined.
Department of Electrical Engineering
Pakistan Institute of Engineering and Applied Sciences
Data Types-> Vectors
The Verilog word for a multi-bit quantity is
a vector. If arithmetic is performed on a vector, the vector value isconsidered to be an unsigned integer.
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Both
nets
and
registers
can
be
declared
as
vectors.
They
are
declared by using a range specifier in the declaration:
wire [msb:lsb] w1;
and reg [msb:lsb] r1;
Both msb and lsb must be constant valued expressions. The bitorder can be either big-endian or little-endian, i.e. both msb
-^
The following statements declare vectors:
reg
[15:0]
accum_lo;
reg
[31:16]
accum_hi;
wire
[1:48]
system_bus;
wire
[0:7]
bus_slice0,
bus_slice1,
bus_slice2;
Vectors -> Operations
: There are four operations that can be
performed on vectors
-^
Bit-Select
-^
Part-Select
-^
Concatenation
-^
Repeat Concatenation
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Department of Electrical Engineering
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Bit-select
is the Verilog term for accessing a single bit of a vector.
You can use a vector bit-select on either the right-hand side or theleft-hand side of an assignment.
-^
It is permissable for the bit-select index to be an expression in aright-hand side expression, or in the left-hand side bit-select inprocedural code. However, if the bit-select appears on the left-handside in declarative code (i.e. in a continuous assignment), the bit-select index must be a constant-valued expression.
-^
If the bit-select index is out of range of the vector, then the result is x.The result is also x if the index itself is x. It is illegal to apply bit-select to a real register.
-^
The following are examples of bit-select operations:^ assign w = vec[3];^ assign vec[5] =
f(x,y,z);
... x = vec[f(x,y,z)]; vec[y] = z;