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An in-depth exploration of cache coherence in multi-core architecture. The lecture covers four different organizations of shared memory systems: bus-based smp, shared cache, dancehall, and distributed shared memory. The advantages and disadvantages of each organization and explains the concept of cache coherence to ensure that all processors see the same memory values. The lecture also includes examples and explanations of write-through and writeback caches, as well as the importance of ordering memory operations.
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Shared cache
The switch is a simple controller for granting access to cache banks
Interconnect is between the processors and the shared cache Which level of cache hierarchy is shared depends on the design: Chip multiprocessors today normally share the outermost level (L2 or L3 cache) The cache and memory are interleaved to improve bandwidth by allowing multiple concurrent accesses Normally small scale due to heavy bandwidth demand on switch and shared cache
Bus-based SMP
Scalability is limited by the shared bus bandwidth
Interconnect is a shared bus located between the private cache hierarchies and memory controller The most popular organization for small to medium-scale servers Possible to connect 30 or so processors with smart bus design Bus bandwidth requirement is lower compared to shared cache approach Why?
In all four organizations caches play an important role in reducing latency and bandwidth requirement If an access is satisfied in cache, the transaction will not appear on the interconnect and hence the bandwidth requirement of the interconnect will be less (shared L1 cache does not have this advantage) In distributed shared memory (DSM) cache and local memory should be used cleverly Bus-based SMP and DSM are the two designs supported today by industry vendors In bus-based SMP every cache miss is launched on the shared bus so that all processors can see all transactions In DSM this is not the case
Possible to combine bus-based SMP and DSM to build hierarchical shared memory Sun Wildfire connects four large SMPs (28 processors) over a scalable interconnect to form a 112p multiprocessor IBM POWER4 has two processors on-chip with private L1 caches, but shared L2 and L3 caches (this is called a chip multiprocessor); connect these chips over a network to form scalable multiprocessors Next few lectures will focus on bus-based SMPs only
Intuitive memory model For sequential programs we expect a memory location to return the latest value written to that location For concurrent programs running on multiple threads or processes on a single processor we expect the same model to hold because all threads see the same cache hierarchy (same as shared L1 cache) For multiprocessors there remains a danger of using a stale value: in SMP or DSM the caches are not shared and processors are allowed to replicate data independently in each cache; hardware must ensure that cached values are coherent across the system and they satisfy programmers' intuitive memory model
Assume a write-through cache i.e. every store updates the value in cache as well as in memory P0: reads x from memory, puts it in its cache, and gets the value 5 P1: reads x from memory, puts it in its cache, and gets the value 5 P1: writes x=7, updates its cached value and memory value P0: reads x from its cache and gets the value 5 P2: reads x from memory, puts it in its cache, and gets the value 7 (now the system is completely incoherent) P2: writes x=10, updates its cached value and memory value
Need to formalize the intuitive memory model In sequential programs the order of read/write is defined by the program order; the notion of “last write” is well-defined For multiprocessors how do you define “last write to a memory location” in presence of independent caches? Within a processor it is still fine, but how do you order read/write across processors?
Memory operation : a read (load), a write (store), or a read-modify-write Assumed to take place atomically A memory operation is said to issue when it leaves the issue queue and looks up the cache A memory operation is said to perform with respect to a processor when a processor can tell that from other issued memory operations A read is said to perform with respect to a processor when subsequent writes issued by that processor cannot affect the returned read value A write is said to perform with respect to a processor when a subsequent read from that processor to the same address returns the new value
A memory operation is said to complete when it has performed with respect to all processors in the system Assume that there is a single shared memory and no caches Memory operations complete in shared memory when they access the corresponding memory locations Operations from the same processor complete in program order: this imposes a partial order among the memory operations Operations from different processors are interleaved in such a way that the program order is maintained for each processor: memory imposes some total order (many are possible)
P0: x=8; u=y; v=9; P1: r=5; y=4; t=v; Legal total order: x=8; u=y; r=5; y=4; t=v; v=9; Another legal total order: x=8; r=5; y=4; u=y; v=9; t=v;
“Last” means the most recent in some legal total order A system is coherent if Reads get the last written value in the total order All processors see writes to a location in the same order