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Example 1: (expression evaluation)
Write an SRC assembly language program to evaluate the expression:
z = 4(a +b) – 16(c+58) Your code should not change the source operands
Solution: Notice that the SRC does not have a multiply instruction.
We may solve the problem by assuming that a multiply instruction,
similar to the add instruction, exists. Instead, we will make use of the
fact that multiplication with powers of 2 can be achieved by repeated
shift left operations. A possible solution is give below:
ld R1, c ; c is a label used for a memory location
addi R3, R1, 58 ; R3 contains (c+58)
shl R7, R3, 4 ; R7 contains 16(c+58)
ld R4, a
ld R5, b
add R6, R4, R5 ; R6 contains (a+b)
shl R8, R6, 2 ; R8 contains 4(a+b)
sub R9, R7, R8 ; the result is in R
st R9, z ; store the result in memory location z
Note: the memory labels a,b,c and z can be defined by using
assembler direectives like .dw or .db, etc. in the source file. Docsity.com
Another solution … Note: If we assume a mul instruction in the instruction set of the SRC, the shl will be replaced by the mul instruction as shown below:
ld R1, c ; c is a label used for a memory location
addi R3, R1, 58 ; R3 contains (c+58)
mul R7, R3, 4 : R7 contains 16(c+58)
ld R4, a
ld R5, b
add R6, R4, R5 ; R6 contains (a+b)
mul R8, R6, 2 ; R8 contains 4(a+b)
sub R9, R7, R8 ; the result is in R
st R9, z ; store the result in memory location z
Note: the memory labels a,b,c and z can be defined by using
assembler direectives like .dw or .db, etc. in the source file.
Source program with directives
.ORG 200 ; start the next line at address 200
a: .DW 1 ; reserve one word for the label a in the memory
b: .DW 1 ; same for b… this will be at address 204
c: .DW 1 ; the 32-bit memory word c will be at address 208
z: .DW 1 ; reserve one word for the result also
.ORG 400 ; start the code at address 400
; all numbers are in decimal unless otherwise stated
ld R1, c ; c is a label used for a memory location
addi R3, R1, 58 ; R3 contains (c+58)
shl R7, R3, 4 : R7 contains 16(c+58)
ld R4, a
ld R5, b
add R6, R4, R5 ; R6 contains (a+b)
shl R8, R6, 2 ; R8 contains 4(a+b)
sub R9, R7, R8 ; the result is in R
st R9, z ; store the result in memory location z
This is the way a
program will appear
in the source file.
Most assemblers
require that the file
be saved with a .asm
extension.
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Solution:
.ORG 200 ; start the next line at address 200
a: .DW 1 ; reserve one word for the label a in the memory
b: .DW 1 ; same for b… this will be at address 204
c: .DW 1 ; the 32-bit memory word c will be at address 208
z: .DW 1 ; reserve one word for the result also
.ORG 400 ; start the code at address 400
We conclude the following from the above statements:
Label Address Value a 200 unknown b 204 unknown c 208 unknown z 212 unknown
Memory
Address
Memory
Contents
200 unknown 204 unknown 208 unknown 212 unknown … ,,, 400 ld R1, c 404 addi R3, R1, 58 408 shl R7, R3, 4 412 ld R4, a 416 ld R5, b 420 add R6, R4, R 424 shl R8, R6, 2 428 sub R9, R7, R 432 st R9, z
Memory
Map for the
SRC
example
program
400 ld R1, c
Notice that this is a type C instruction with
the rb field missing
400 ld R1, c
Regist er Code Regist er Code Regist er Code Regist er Code R0 00000 R8 01000 R16 10000 R24 11000 R1 00001 R9 01001 R17 10001 R25 11001 R2 00010 R10 01010 R18 10010 R26 11010 R3 00011 R11 01011 R19 10011 R27 11011 R4 00100 R12 01100 R20 10100 R28 11100 R5 00101 R13 01101 R21 10101 R29 11101 R6 00110 R14 01110 R22 10110 R30 11110 R7 00111 R15 01111 R23 10111 R31 11111
- Pick op code corresponding to ld from SRC table
la 0 0 1 0 1 lar 0 0 1 1 0 ld 0 0 0 0 1 ldr 0 0 0 1 0 neg 0 1 1 1 1 nop 0 0 0 0 0 not 1 1 0 0 0 or 1 0 1 1 0 ori 1 0 1 1 1 shc 1 1 1 0 1 shc 1 1 1 0 1 shl 1 1 1 0 0 shl 1 1 1 0 0 shr 1 1 0 1 0 shr 1 1 0 1 0 shra 1 1 0 1 1 shra 1 1 0 1 1 st 0 0 0 1 1 stop 1 1 1 1 1 str 0 0 1 0 0 sub 0 1 1 1 0
- Pick register code corresponding to R from register table
400 ld R1, c
Regist er Code Regist er Code Regist er Code Regist er Code R0 00000 R8 01000 R16 10000 R24 11000 R1 00001 R9 01001 R17 10001 R25 11001 R2 00010 R10 01010 R18 10010 R26 11010 R3 00011 R11 01011 R19 10011 R27 11011 R4 00100 R12 01100 R20 10100 R28 11100 R5 00101 R13 01101 R21 10101 R29 11101 R6 00110 R14 01110 R22 10110 R30 11110 R7 00111 R15 01111 R23 10111 R31 11111
- Pick op code corresponding to ld from SRC table
la 0 0 1 0 1 lar 0 0 1 1 0 ld 0 0 0 0 1 ldr 0 0 0 1 0 neg 0 1 1 1 1 nop 0 0 0 0 0 not 1 1 0 0 0 or 1 0 1 1 0 ori 1 0 1 1 1 shc 1 1 1 0 1 shc 1 1 1 0 1 shl 1 1 1 0 0 shl 1 1 1 0 0 shr 1 1 0 1 0 shr 1 1 0 1 0 shra 1 1 0 1 1 shra 1 1 0 1 1 st 0 0 0 1 1 stop 1 1 1 1 1 str 0 0 1 0 0 sub 0 1 1 1 0
- Pick register code corresponding to R from register table
- Notice that there is no register coded in the rb field. So, use 5 0’s
400 ld R1, c
Regist er Code Regist er Code Regist er Code Regist er Code R0 00000 R8 01000 R16 10000 R24 11000 R1 00001 R9 01001 R17 10001 R25 11001 R2 00010 R10 01010 R18 10010 R26 11010 R3 00011 R11 01011 R19 10011 R27 11011 R4 00100 R12 01100 R20 10100 R28 11100 R5 00101 R13 01101 R21 10101 R29 11101 R6 00110 R14 01110 R22 10110 R30 11110 R7 00111 R15 01111 R23 10111 R31 11111
- Pick op code corresponding to ld from SRC table
la 0 0 1 0 1 lar 0 0 1 1 0 ld 0 0 0 0 1 ldr 0 0 0 1 0 neg 0 1 1 1 1 nop 0 0 0 0 0 not 1 1 0 0 0 or 1 0 1 1 0 ori 1 0 1 1 1 shc 1 1 1 0 1 shc 1 1 1 0 1 shl 1 1 1 0 0 shl 1 1 1 0 0 shr 1 1 0 1 0 shr 1 1 0 1 0 shra 1 1 0 1 1 shra 1 1 0 1 1 st 0 0 0 1 1 stop 1 1 1 1 1 str 0 0 1 0 0 sub 0 1 1 1 0
- Pick register code corresponding to R from register table
- Notice that there is no register coded in the rb field. So, use 5 0’s
4.The value of the label c is provided by the assembler, and should be converted to 17 bits Label Address Value a 200 unknown b 204 unknown c 208 unknown z 212 unknown
- The complete instructio n
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400 ld R1, c
Regist er Code Regist er Code Regist er Code Regist er Code R0 00000 R8 01000 R16 10000 R24 11000 R1 00001 R9 01001 R17 10001 R25 11001 R2 00010 R10 01010 R18 10010 R26 11010 R3 00011 R11 01011 R19 10011 R27 11011 R4 00100 R12 01100 R20 10100 R28 11100 R5 00101 R13 01101 R21 10101 R29 11101 R6 00110 R14 01110 R22 10110 R30 11110 R7 00111 R15 01111 R23 10111 R31 11111
- Pick op code corresponding to ld from SRC table
la 0 0 1 0 1 lar 0 0 1 1 0 ld 0 0 0 0 1 ldr 0 0 0 1 0 neg 0 1 1 1 1 nop 0 0 0 0 0 not 1 1 0 0 0 or 1 0 1 1 0 ori 1 0 1 1 1 shc 1 1 1 0 1 shc 1 1 1 0 1 shl 1 1 1 0 0 shl 1 1 1 0 0 shr 1 1 0 1 0 shr 1 1 0 1 0 shra 1 1 0 1 1 shra 1 1 0 1 1 st 0 0 0 1 1 stop 1 1 1 1 1 str 0 0 1 0 0 sub 0 1 1 1 0
- Pick register code corresponding to R from register table
- Notice that there is no register coded in the rb field. So, use 5 0’s
- Finally, the value of the label c is provided by the assembler, and should be converted to 17 bits Label Address Value a 200 unknown b 204 unknown c 208 unknown z 212 unknown
- The complete instructio n
0 8 4 0 0 0 D 0 h
- And in hexadeximal
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404 addi R3, R1, 58
Type C instruction with the rc field missing
1. Pick op code
corresponding to addi from SRC table
- la - lar - ld - ldr - neg - nop - not - or - ori - shc - shc - shl
- shl
- shr
- shr
- shra
- shra - st
- 404 addi R3,R1, - la - lar - ld - ldr - neg - nop - not - or - ori - shc - shc - shl - shl - shr - shr
404 addi R3,R1,
Regist er Code Regist er Code Regist er Code Regist er Code R0 00000 R8 01000 R16 10000 R24 11000 R1 00001 R9 01001 R17 10001 R25 11001 R2 00010 R10 01010 R18 10010 R26 11010 R3 00011 R11 01011 R19 10011 R27 11011 R4 00100 R12 01100 R20 10100 R28 11100 R5 00101 R13 01101 R21 10101 R29 11101 R6 00110 R14 01110 R22 10110 R30 11110 R7 00111 R15 01111 R23 10111 R31 11111
- Pick op code corresponding to addi from SRC table 01101 la 0 0 1 0 1 lar 0 0 1 1 0 ld 0 0 0 0 1 ldr 0 0 0 1 0 neg 0 1 1 1 1 nop 0 0 0 0 0 not 1 1 0 0 0 or 1 0 1 1 0 ori 1 0 1 1 1 shc 1 1 1 0 1 shc 1 1 1 0 1 shl 1 1 1 0 0 shl 1 1 1 0 0 shr 1 1 0 1 0 shr 1 1 0 1 0 shra 1 1 0 1 1 shra 1 1 0 1 1 addi 0 1 1 0 1 stop 1 1 1 1 1 str 0 0 1 0 0 sub 0 1 1 1 0
- Pick register code corresponding to R3 from register table (^00011 )
- Pick register code corresponding to R1 from register table
- Notice that there is no register coded in the rc field. Use five zeros instead.
404 addi R3,R1,
Regist er Code Regist er Code Regist er Code Regist er Code R0 00000 R8 01000 R16 10000 R24 11000 R1 00001 R9 01001 R17 10001 R25 11001 R2 00010 R10 01010 R18 10010 R26 11010 R3 00011 R11 01011 R19 10011 R27 11011 R4 00100 R12 01100 R20 10100 R28 11100 R5 00101 R13 01101 R21 10101 R29 11101 R6 00110 R14 01110 R22 10110 R30 11110 R7 00111 R15 01111 R23 10111 R31 11111
- Pick op code corresponding to addi from SRC table
la 0 0 1 0 1 lar 0 0 1 1 0 ld 0 0 0 0 1 ldr 0 0 0 1 0 neg 0 1 1 1 1 nop 0 0 0 0 0 not 1 1 0 0 0 or 1 0 1 1 0 ori 1 0 1 1 1 shc 1 1 1 0 1 shc 1 1 1 0 1 shl 1 1 1 0 0 shl 1 1 1 0 0 shr 1 1 0 1 0 shr 1 1 0 1 0 shra 1 1 0 1 1 shra 1 1 0 1 1 addi 0 1 1 0 1 stop 1 1 1 1 1 str 0 0 1 0 0 sub 0 1 1 1 0
- Pick register code corresponding to R3 from register table
- Pick register code corresponding to R1 from register table
- Use the binary code for immediate data
