CMP3006 Embedded Systems Programming Lecture 9: Interfacing with I2C, Lecture notes of Embedded Systems Programming

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CMP

EMBEDDED

SYSTEMS

PROGRAMMING

LECTURE 9 INTERFACING: I2C

Atmega 328 Pinout

I2C …

Master Transmit CLK ( transmitter or receiver)

Receiver does not change the level of SDA unless it wants to generate ACK

Note: Receiver can be Master or Slave

Bit Format

Each data bit transferred on the SDA line is synchronized by a high-to-low pulse

of clock on the SCL line.

Data line can change only when the clock line is low. Stop and Start conditions

are exceptions.

Repeated Start

If a master,which has the control of the bus, wishes to initiate a new transfer

and does not want to release the bus before starting the new transfer, it issues a

new START condition between a pair of START and STOP conditions.

Typical data transmission

Packet Format

Packet Types:

 Address Packet

 Data Packet

Address packet

Started by a Start Condition

 7 bits address, MSB first

 Define R/W

 ACK or NACK

Clock Stretching

If an addressed slave device is not ready to process more data, it will stretch

the clock by holding the clock line (SCL) low after receiving (or sending) a bit of

data.

Arbitration

it is possible that two or more masters initiate a transmission at about the

same time

 Each transmitter has to check the level of the bus and compare it with the level it expects

 if it doesn't match, that transmitter has lost the arbitration, and will switch to slave mode

I

C unit in AVR

Bus Interface Unit

 detects and generates START, REPEATED START and STOP conditions.

 detects arbitration

 controls sending or receiving ACK transfers packets of data or address.

Bit Rate Generation Unit

 controls the frequency of the system clock (SCL) when operating in a master mode

I

C unit in AVR

Address Match Unit

 Compares the received address byte with the 7-bit address in TWI address register and

informs the control unit upon an address match.

Control Unit

 controls the TWI module and generates responses according to settings in the TWI control

register

 sets the contents of the status register

 according to current state.

TWAR (TWI Address Register)

TWA6-0 (TWI slave Address)

TWGCE (TWI General Call Recognition Enable bit)

◦ 1: Answer to general call

TWI Control Register

TWINT (TWI Interrupt Flag)

TWEA (TWI Enable Acknowledge Bit)

 1:ACK, 0:NACK

TWSTA (TWI Start condition bit)

TWSTO (TWI Stop condition bit)

TWWC (TWI Write Collision flag)

TWEN (TWI Enable bit)

TWIEN (TWI Interrupt Enable)