SPI Interfacing: Atmega 328 Pinout and SPI Communication, Lecture notes of Embedded Systems Programming

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CMP

EMBEDDED

SYSTEMS

PROGRAMMING

LECTURE 8 INTERFACING:SPI

Atmega 328 Pinout

Analog Interfacing

ADC

 Converts Analog Signal to Digital number

Sensor

Component

Analog Voltage (0V - 5V)

Single Bit

Button

 Two state (HIGH/LOW)

Sensor/

Button

HIGH/LOW

Asynchronous Communication

UART (Serial Port)

No synchronization on sending & recieveing

 Both sides must agree on the transmission speed (e.g. 9600bps)

 They are supposed to run at precisely the same rate

Synchronous Communication

SPI, I2C

Synchronization on sending & recieveing

 Uses separate line for clock signal to synchronize

 They run at precisely the same rate with the clock signal

SPI: Serial Peripheral Interface

Read and Write happens at the same time

Uses Shift Registers

SPI: Serial Peripheral Interface

SPI OVERVIEW – THE REGISTERS

SPI REGISTERS

SPI Control Register – You configure the SPI subsystem

SPDR: SPI Data Register – Once enabled (SPE = 1), writing to the SPI Data

Register (SPDR) begins SPI transfer.

SPSR : SPI Status Register

The SPSR register contains the SPIF flag. The flag is set when 8 data bits have been

transferred from the master to the slave.

The WCOL flag is set if the SPI Data Register (SPDR) is written during the data transfer

process.

Setting bit SPE bit enables the SPI

SPCR

SPI Interrupt Enable = 0

 This bit causes the SPI interrupt to be executed if the SPIF bit in the SPSR Register is set and if the

Global Interrupt Enable bit in SREG is set. For our design example we will be polling the SPIF bit.

Consequently, we will leave the SPIE bit in its default (SPIE = 0) state.

SPI Enable = 1

When the SPE bit is one, the SPI is enabled. This bit must be set to enable any SPI operations.

Data Order = 0 When the DORD bit is one (DORD = 1), the LSB of the data word is transmitted

first, otherwise the MSB of the data word is transmitted first.

MSTR: Master/Slave Select = 1

This bit selects Master SPI mode when set to one, and Slave SPI mode when cleared

SPCR

Clock Polarity = 0 and Clock Phase = 0

The Clock Polarity (CPOL) and Clock Phase (CPHA) bits define how serial data is transferred

between the master and the slave.

SS Pin

Master Mode

You can set the direction to output and SPI will not control the pin

If you set the direction to input, It should be externally pulled up

 if you make it externally low, the SPI module stops working in master mode and switches to slave mode by clearing

the MSTR bit in SPCR, and then sets the SPIF bit in SPSR.

Slave Mode

SS pin is always input and you can not control it by software.

You should hold it externally low to activate the SPI.

When SS is driven high, SPI is disabled and all pins of SPI are input. Also the SPI module will

immediately clear any partially received data in the shift register BUT IT WILL NOT BE

DISABLED

Master Operating Mode

Set the MSTR bit to one

Set SCK frequency by setting the values of SPI2X, SPR1, and SPR

Set the SPI mode. If not set, it is 0.

Enable SPI by setting the SPIE bit to one

Write a byte to the SPI Data Register (SPDR)

Poll the SPIF flag. Data transfer is finished when it changes to one.

read the received byte from SPDR before the next byte arrives.

Note: After the transmission, the byte in the Master shift register is moved to the Slave Shift

register and the Byte in the Slave shift register is moved to the Master shift register. It means

that send and received happens at the same time. If you only want to read a byte, you should

transmit a dummy byte like 0xff and then read the received data!