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ELEX 2117 : Digital Techniques 2 2024 Winter Term
Analog Interfaces
A Digital-to-Analog converter (DAC or D/A) converts discrete (“digital”) signals to continuous (“analog”) ones. A Digital- to-Analog converter (ADC or A/D) does the reverse. This lecture describes their specifications and some common imple- mentations. After this lecture you should be able to solve problems involving: sampling rate vs signal frequencies; number of bits vs resolution and quantization SNR; clock rate, sample rate and resolution for binary-weighted DAC, PWM DAC, flash ADC, SAR ADC.
Introduction
Signals are time-varying voltages or currents. Analog signals are continuous in time and voltage. Exam- ples include the voltages produced by microphones and image sensors, the outputs of strain gauges that measure forces,the currents that control electric mo- tors, the radio-frequency signals on antennas used for wireless communication, and many others.
In most cases these analog signals are converted to, or from, a digital form for processing. This is because processing digital representations of these signals is less expensive, consumes less power and is more pre- cise than processing signals in their analog form.
The diagram below shows the various functions in- volved in processing analog signals in digital form. These will be described in this lecture.
amplifier
anti-aliasingfilter ADC processordigital interfacesdigital reconstructionfilter DAC
amplifier
outputsignal
analog "front-end"
signal^ input
low-pass filters
Sampled Waveforms
To represent signals in digital form, the analog sig- nal is sampled (measured) at a regular rate called the “sampling rate.” Each sample is then converted into a binary number with a fixed number of bits. Thus the signal becomes discrete in both time and voltage. The circuit that does this is called an analog-to-digital converter (ADC or A/D).
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A digitized signal can be converted to a continous signal by generating a step-like waveform with the re- quired levels at the required sampling rate. The cir- cuit that does this is called a digital-to-analog con- verter (abbreviated as DAC or D/A). This waveform is then smoothed into a continous signal by low-pass filtering with a “reconstruction” filter.
voltage
time
reconstructed continuous analog signal (^) discrete-time discrete-amplitude digital signal
Sampling Rate and Resolution
The two most important characteristics of a digitized signal are its sampling rate and resolution. The sampling rate (or frequency) must be high enough to be able to accurately reconstruct the origi- nal signal. The Nyquist sampling theorem states that a signal can be exactly reconstructed if it is sampled at more than twice the highest frequency of the sig- nal. If the sampling rate is too low then frequency components will be “aliased” and appear at a differ- ent, lower frequency. To avoid this, the analog signal can be low-pass filtered with an “anti-aliasing” filter to remove frequency components above half of the sampling rate.
lec8.tex 1 2024-03-21 10:
Exercise 1: Draw a sine wave and indicate two sets of sampling points at twice the frequency of the sine wave: one that demon‑ strates aliasing and one that does not. Is it sufficient to sample at twice the highest frequency of the analog signal? Exercise 2: What minimum sampling rate would be required to dig‑ itize a 10 kHz square wave if you wanted to include frequency com‑ ponents up to the 7’th harmonic (at 70 kHz)? Digitized signals are represented as 𝑛-bit binary numbers where each of the 2 𝑛^ possible values repre- sents a different voltage. If the range of voltage lev- els that can be quantized is 𝑉 then the difference be- tween each quantized voltage level is Δ = 𝑉/ 2 𝑛. For example, if 𝑉 = 1 V and 𝑛 = 3 then Δ = 1 / 8 = 0.125 V. Voltages between 0 and 0.125 are encoded as 000, voltages between 0.125 and 0.25 are encoded as 001, and so on, as shown below:
000
001
010
011
100
101
110
111
0
voltage (^) encoding
The “resolution” of an ADC can refer to either the number of bits, 𝑛, (e.g. “a 10-bit resolution ADC”) or the difference between adjacent voltage levels, Δ (e.g. “a resolution of 1 mV”). Units determine which definition is being used. Exercise 3: A signal with range of ±3 V must be quantized so that the quantization error is less than 1 mV. What minimum number of bits of resolution is required? Quantizing a signal requires that the signal be rounded off to the nearest quantized voltage level. Rounding has the same effect as adding a “quanti- zation noise” error to each sample. For some ap- plications, the ratio of signal power to the power of this quantization noise is a useful specification. This quantization signal-to-noise ratio (SNR) for a full- scale sine wave input is 1.76 + 6𝑛 dB^1. Exercise 4: A signal‑to‑noise power ratio of about 48 dB is con‑ sidered “good enough” for speech communication. Approximately
(^1) For other waveforms the value depends on the type of signal being digitized.
how many bits per sample are required to obtain this quantization SNR? Exercise 5: When quantizing a full‑scale sine wave, what quantiza‑ tion SNR would be achieved with a resolution of 12 bits? What if the signal’s voltage range was only half of the full‑scale range? If the SNR is known then this equation can be solved for a specification known as the effective num- ber of bits (ENOB), 𝑛. ENOB may include other ef- fects, such as distortion. Exercise 6: A DAC outputs a digitized 1 kHz sine‑wave signal. The analog output is analyzed and the power at 1 kHz is found to be 1 W while the power at all other frequencies adds up to 10 mW. What is the ENOB? Other specifications that are important for specific applications include: monotonic Each increase in digital value also re- sults in an increase of the analog value. linearity The maximum deviation from an ideal straight-line relationship between digital and analog values distortion There are several ways of measuring dis- tortion, often in terms of the frequency compo- nents generated by the distortion.
Digital to Analog Converters
Binary‑Weighted DAC
We can use each bit of the quantized signal to con- trol the addition of binary-weighted voltages to the output. Given a reference voltage 𝑉ref/2, the most- significant bit controls adding a value of 𝑉ref/2 to the output, the next-most-significant bit controls adding a value of 𝑉ref/4, and so on. Typical implementations use two resistor values in an “R-2R” voltage divider network. A 4-bit example is:
2R
R
2R
R
2R
R
2R
V 0 V 1 V 2
2R
Vout
V 3
2R
3 4 5
𝑉out = ( 𝑉^3 2
+ 𝑉^2
+ 𝑉^1
+ 𝑉^0
−
−
−
encoder
2
Vref
Vin
1Vref/
2Vref/
3Vref/
This is the fastest type of ADC – the sampling rate is equal to the clock rate – but it is the most expensive as the complexity increases exponentially with 𝑛. Exercise 11: Draw a diagram showing the voltage ranges, the com‑ parator outputs and the binary output for the 4‑bit flash ADC above.
SAR ADC
A Successive Approximation Register (SAR) DAC uses a state machine to progressively test the in- put voltage against thresholds output by a DAC. The threshold voltages are determined by a state machine that does a binary search for the 𝑛-bit DAC output that is just higher than the input voltage. A SAR ADC can do one conversion per 𝑛 clock cy- cles and its complexity increases linearly with 𝑛. Exercise 12: A SAR ADC using a 4‑bit DAC with a full‑scale range of 0 to 7.5 V digitizes a 5.25 V signal. What voltages will the DAC output?
Sigma‑Delta ADC
A simple Sigma-Delta ADC, shown below, consists of a low-pass filter (LPF) whose output is compared to the analog input. If the analog input is higher than the LPF output, a positive pulse is output to the LPF, otherwise a zero is output. The LPF integrates these pulses in the same way as a Sigma-Delta DAC. A counter measures the number of pulses per unit time which is proportional to the analog input.
counter
Vin −
comparator n D Q
clock
low-pass filter Vref or 0
A Sigma-Delta ADC requires clock rates much higher than (e.g. 100 times)^3 the sampling rate but is inexpensive because it does not require accurate ana- log components (e.g. the accurate resistors in the R- 2R network used in a SAR ADC).
Dual‑Slope ADC
−
Vin -Vref (^) Vthreshold^ counter^
n
T
Vintegrator
time t 2
V 1
V 2
t 1
Vthreshold
A dual-slope ADC integrates the input for a fixed duration (𝑇) and measures the time required to in- tegrate a negative reference voltage until the integra- tor is discharged. The ratio 𝑡/𝑇 is the ratio of 𝑉in/𝑉ref. This approach eliminates the dependence on several analog components (integrator 𝑅 and 𝐶, comparator thresholds, and clock rates). A dual-slope ADC is slow but inexpensive and po- tentially accurate. It is commonly used in instrumen- tation. Exercise 13: What is the slope of an integrator, in V/s, when charg‑ ing a 100 nF capacitor with 5 V through a 100 kΩ resistor?
(^3) The required oversampling ratio, the ratio of clock rate to sampling rate, depends on the desired ENOB and sigma-delta ar- chitecture.
Timing Analysis
Exercise 1 :
The diagram above shows an oscilloscope screen capture that in- cludes one period of an active-low digital waveform. The scale on the horizontal axis is 20 ns per division. What are: the rise time, period, positive pulse width and duty cycle?
Exercise 2 :
input 1 input 2 output 1 output 2
A B C D
Label the specifications A through D as requirements or guaranteed responses. Which specifications are measured to a signal being in a high-impedance state? Which are measured from a rising edge only? From either?
Exercise 3 : Is 𝑡PD a requirement or a guaranteed response?
Exercise 4 : Is 𝑡SU a requirement or a guaranteed response? How
about 𝑡H?
ELEX 2117 : Digital Techniques 2 2024 Winter Term
Hierarchical Design
This lecture describes Verilog modules and parameters. After this lecture you should be able to: declare modules with parameters and ports, and instantiate modules using posi- tional, named and wildcard parameters and signals.
Modules
Simple things are easier to design and test than com- plex ones. Thus it’s good practice to divide designs into smaller parts^1. These can often be re-used. Many designs incorporate complex parts designed by others (e.g. processors, memories and interfaces), called design IP (“Intellectual Property”). In Verilog each part is a module. Modules describe logic that can be “instantiated” (duplicated and in- serted into) another module:
instantiating module
instantiated module
signal (^) port
name:id
The module’s interfaces are defined by a header describing ports and parameters. Ports are in, out or inout (bidirectional) signals while parameters are values that can customize each instance of a module. The module’s body contains additional signal decla- rations and parallel (concurrently executing) state- ments between module and endmodule. These de- fine the structure or behaviour of the module. Here’s an example of a module named bits that defines an nb-bit register:
module bits #(parameter nb = 1) ( input logic [ nb - 1 : 0 ] d , output logic [ nb - 1 : 0 ] q , input logic clock ) ; always_ff @(posedge clock) q <= d ;
endmodule
(^1) How small? A good rule of thumb is to make sure each part can be described on a single page.
The parameter nb has a default value of 1 which is used if a value is not specified when this module is instantiated. There are two input ports (named d and clock) and one output port (named q). A module instantiation starts with the name of the module followed by parameter values (if any), an in- stance name (to identify individual instances of the same module), and a description of how to connect signals in the instantiating module to the ports in the instantiated module. For example, the statement: bits #(4) b0 (a,b,c) ; would instantiate a bits module giving the first pa- rameter a value 4, giving this instance the name b0, and connect the signals a, b and c in the instantiat- ing module to the corresponding ports in a copy (an instantiation) of the bits module (in this case, d, q and clock respectively). Exercise 1: Draw a diagram for this instantiation of the bits mod‑ ule. Label the module, instance, signal and port names as in the diagram above. An 8-bit, 3-stage shift register could be built using three bits modules: sr3bytes
newest oldest
bits:b d q clock
d q clock
d q clock clock
a b
bits:b1 bits:b
module sr3bytes ( input logic [ 7 : 0 ] newest , output logic [ 7 : 0 ] oldest , input logic clock ) ; localparam nbits = 8 ; logic [ nbits - 1 : 0 ] a , b ; // matching by order bits #( nbits) b0 ( newest , a , clock) ; // matching by name (order does not matter)
lec9.tex 1 2024-03-28 08:
clock
bits:b
clock d[7..0]
q[7..0]
bits:b clock d[7..0]
q[7..0]
bits:b
clock d[7..0]
q[7..0]
newest[7..0]
oldest[7..0]
Figure 1: Shift Register Synthesis
bits #(. nb ( nbits)) b1 (. q ( b) ,. clock ,. d ( a)) ; // wildcards for names that match bits #(. nb ( nbits)) b2 (. d ( b) ,. q ( oldest) ,.* ) ;
endmodule
Exercise 2: Identify the module instantiation statements in the code above. For each one, what is the instantiated module’s name? The instance name? When one module is instantiated in another, a sig- nal can be connected to module port by:
- port order (signal),
- port name and explicit signal name (.port(signal)),
- port name only – connecting to the matching signal name (.port),
- a wildcard that matches all remaining matching port and signal names (.*).
The signal name can be an expressions (e.g. word[15:8]) instead of a signal. Matching of values to parameters can be done by order (value) or explicitly, .parameter(value). The synthesis result, shown above, is as expected.
Exercise 4 : All else being equal, by how much would we expect to decrease power consumption when reducing logic levels from 5 V to 3.3 V? What would be the effect on power consumption in reducing the clock frequency from 50 MHz to 1 MHz?
Exercise 5 : What are the active-state current and the RC time con-
stant for a wired-or interrupt-request line using a 10kΩ resistor pulling
up a circuit with 50 pF capacitance to 3.3 V?
Exercise 6 : How many square mm of PCB area does each pack- age require? Which packages have their pins accessible when the package is placed on the PCB?
ELEX 2117 : Digital Techniques 2 2024 Winter Term
Implementation Technologies
After this lecture you should be able to: explain the growth of digital electronics; select software versus hardware and PLDs versus ASICs to solve a particular problem; explain the terms: Moore’s Law, ASIC, CPLD, FPGA, feature size, VLSI, fabless, wafer, die, NRE, FPGA, LE and LUT.
Hardware vs Software
When would you design hardware instead of writing software? Software-based solutions are generally preferred due to:
- Lower Development Cost. Existing hardware (e.g. a microcontroller) can be customized for a new application with software.
- Shorter Development Time. Software can be coded more quickly than equivalent hardware can be designed.
- Lower Risk. Errors can be fixed and new fea- tures added by deploying a new version of the software.
- More Expertise. There are many more^1 software developers than digital hardware engineers.
However, there are several situations for which a hardware solution is typically necessary.
Speed
A processor running software will take one or more clock cycles for each operation (instruction). The operations required (I/O, arithmetic/logic, memory access, etc.) to complete time-critical func- tions will depend on the task and can usually be es- timated. We can then multiply by the clock period to estimate the processing latency (delay) and compare to the time available. If the required number of operations can be com- pleted in the time available for the task, then a software-based solution is possible, and often pre- ferred. Otherwise, a hardware processor (or co- processor) will be needed.
(^1) Probably more than 10 times as many based on a comparison of Statistics Canada NOC 2174 (programmers) and 2147 (com- puter engineers).
An example is a GPU (Graphics Processing Unit) that can process multiple pixels per clock cycle.
Energy Consumption
Implementing an algorithm on a CPU will require more cycles and more registers. All else being equal^2 a software solution will consume more energy. Exercise 1: Would you use hardware or software to implement: A one‑off digital clock? A watch whose battery must last for years? A controller for a kitchen appliance? A calculator? An Ethernet in‑ terface? For Cryptocurrency “mining”? For an aircraft’s automated landing system?
Introduction
Digital ICs have increased in complexity at an expo- nential rate over the last 40 years. This growth has been at a rate predicted by “Moore’s Law” – an obser- vation that digital IC complexity per unit area seems to double every 2 to 3 years. Moore’s law does not apply to analog ICs. This is because the die area required for an analog IC (e.g. an op-amp) is determined by factors such as its voltage and power rating rather than by the minimum tran- sistor size. The steady decline in the cost of digital relative to analog electronics has resulted in modern electronic devices implementing almost all functionality using digital rather than analog electronics. The main ex- ception is interface electronics, including power elec- tronics. Digital ICs can be classified by the number of gates or transistors on an IC (e.g. SSI, LSI and VLSI stand- ing for small, large and very large scale integration). Application-specific ICs (ASICs) are ICs designed for a specific application (e.g. a graphics processor for a video card or the WLAN transceiver in a cell phone) (^2) Rarely the case.
lec10.tex 1 2024-04-04 07:
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The main difference is the structure of the com- binational logic – either one 4-input look-up table (LUT) per LE in for Intel CPLDs or a larger pro- grammable logic array (PLA) driving 16 MC for Xil- inx. In both cases a programmable interconnect matrix allows the inputs and outputs of logic blocks to be in- terconnected. A wide range of logic functions can be implemented by configuring the LUTs or PLAs and programming the interconnect matrix. Small CPLDs sell for about $1 or $2 in small quan- tities (e.g. the Intel MAX V 5M40 with 64 I/O pins and 40 LE).
FPGA
Gate arrays were an attempt to bridge the gap be- tween fully custom ICs and PLDs. The idea was that gates would be laid out in predefined locations on the die and only the last few layers of interconnect would need to be customized for each IC thus reducing the number of custom masks needed for each IC and thus the NRE. This approach is no longer popular. This idea developed into a Field-Programmable Gate Array. An FPGA is a PLD that contains a large number (thousands to hundreds of thousands) of simple logic elements similar to those in an Intel CPLD. Note that modern FPGAs have no gates – the logic for each LE is implemented using small memo- ries called look-up tables (LUTs). However, an FPGA’s interconnection resources are more limited than those in a CPLD. In keeping with the idea that multiple LEs will be combined to form multi-bit logic functions, logic elements can be connected to their neighbours in logic array blocks (LABs) and these to row and column interconnect buses:
Direct linkinterconnect from adjacentblock
Direct linkinterconnect to adjacentblock
Row Interconnect
ColumnInterconnect
LAB Local Interconnect
Direct linkinterconnect from adjacentblock
Direct linkinterconnect to adjacentblock
Complex software is required to fit a design into an FPGA and route the signals between logic ele- ments. Because of the multiple levels of intercon- nect the propagation delays are harder to predict than for a CPLD. Even if there is sufficient logic, some de- signs may not ‘fit’ into an FPGA because of insuffi- cient routing resources. Modern FPGAs include special-purpose compo- nents such as RAM, multipliers, PLL clock genera- tors and high-speed serial I/O in addition to general- purpose logic elements. Most modern FPGAs have enough logic elements and memory that they can be configured with a “soft” CPU (e.g. Altera’s Nios and Xilinx’s MicroB- laze). This allows the FPGA to include both soft- ware and hardware functions. Some FPGAs include a (hardware-based, typically ARM) CPU core for appli- cations that require both an SoC and programmable logic. Depending on the version, the FPGA might con- tain between 6 k and 114 k logic elements and be- tween 180 and 530 I/O pins. Smaller FPGAs sell for under $10 in small quantities. However, large high- performance FPGAs, often used for ASIC prototyp- ing, can cost many thousands of dollars. Due to the high I/O count most FPGAs use ball grid array (BGA) packages.
PLD Configuration
Although most CPLDs have on-board non-volatile configuration memory, most FPGAs use volatile con- figuration memory which must be reloaded each time the device powers up. The FPGA can load it- self from an external, typically serial, EEPROM or it can be configured through the JTAG interface. On
larger systems that include processors the FPGA is often configured by software running on the proces- sor and in this case the FPGA configuration can be changed as part of a firmware update.
Technology Selection
PLD vs ASIC
If the decision is to use hardware, when would you use programmable logic instead of designing a cus- tom IC (an ASIC)? In most cases all of the required functionality will already be available as part of an existing “off-the- shelf” ASIC or SoC. For example, many SoCs in- tended for cell phones include peripheral interfaces and graphics accelerators. However, in some cases the required hardware function is not available and in this case a decision must be made whether to design a new IC or use an FPGA. The decision depends on the following fac- tors:
- Performance. This includes clock speed and power consumption. An ASIC (or custom full- custom IC) will execute faster and use less power that the same function programmed into an FPGA.
- Sales volume. The NRE for designing the IC (e.g. masks) must be recovered from sales. If the sales volumes are low then the NRE costs per unit may be too high.
- Time to Market (TTM). It takes many months to design, verify and manufacture a custom IC. If TTM is short then an FPGA may a better option.
- Flexibility. If the functionality of the IC is likely to change then a PLD may be a better option. The design can even be changed in the field after the product has been delivered to the customer.
- Risk. Errors in an IC design will require a “re- spin” of the IC resulting in additional costs and delays. For a small company this can be fatal. Because of the above considerations, FPGAs tend to be used in non-consumer products that have relatively low volumes and are relatively cost- insensitive. Examples of typical application areas in- clude telecommunications infrastructure (e.g. large
Internet routers and cellular base stations), medical equipment (e.g. CAT scanners), military/aerospace (e.g. avionics, satellites), and new applications (e.g. artificial intelligence, quantum computing, au- tonomous vehicles). Exercise 3: Would you use a PLD or ASIC for: A project that had to be completed within a month? That would be expected to sell 100 million units? Whose complete requirements aren’t known? A state‑of‑the‑art general‑purpose CPU?
Exercise 3 : A signal with range of ±3 V must be quantized so that
the quantization error is less than 1 mV. What minimum number of bits of resolution is required?
Exercise 4 : A signal-to-noise power ratio of about 48 dB is con- sidered “good enough” for speech communication. Approximately how many bits per sample are required to obtain this quantization SNR?
Exercise 5 : When quantizing a full-scale sine wave, what quantiza- tion SNR would be achieved with a resolution of 12 bits? What if the signal’s voltage range was only half of the full-scale range?
Exercise 7 : You are using a PWM DAC to convert a 200 VDC supply to a 48 VDC output. The switching frequency is 25 kHz. What is the duration of each PWM pulse?
Exercise 8 : You are designing a PWM DAC and need resolution of 1 mV with a full-scale output of 12 V. How many bits of resolution are required? The pulse frequency is 10 kHz. What is the clock fre- quency?
Exercise 9 : Rank the different DACs described above in terms of sampling rate relative to clock rate and complexity relative to reso- lution.
Exercise 10 :
−
−
−
encoder
2
Vref
V (^) in
1Vref/
2Vref/
3Vref/
Draw a diagram showing the voltage ranges, the comparator out- puts and the binary output for the 4-bit flash ADC above.
