Download ECSE-325 Digital Systems Winter 2025 MIDTERM EXAMINATION Answered Correctly. and more Exams Digital Communication Systems in PDF only on Docsity!
McGILL UNIVERSITY
Department of Electrical and Computer Engineering
ECSE-325 Digital Systems Winter 2025
MIDTERM EXAMINATION
(take-home exam, due 11:59pm Thursday February 27)
Question Part a) mark Part b) mark Total
ALL /14 /26 /
(Knowledge Base) (Design)
Name: _____________________________________________________________
Student Number: ____________________________________________________
Instructions/Please read carefully!
This is an open book exam. You are expected to work by yourself, with no
assistance. No time extensions will be allowed.
You should submit your answers on myCourses in the same way that you did
for the assignments.
Read the questions carefully. If something appears ambiguous, write down
your assumptions.
YOUR NAME:
________________________________________________________________________
Question 1: CMOS Circuits (10 points)
(3 points) a) Write down the Boolean function implemented by the
CMOS circuit shown. Be careful to trace out which transistor is
connected to which. You do not need to simplify.
ANSWER: OUT(A,B,K) = !(!K(!A!B+AB)+K(!AB+A!B)) = A xor B xor K (this can be written in different ways, depending on which variables you group together)
YOUR NAME:
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It is easiest to design the pullup network, remembering to invert the inputs.
Y = !A!B!C + !A!BC + !AB!C + A!B!C
YOUR NAME:
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Question 2: Programmable Logic Devices (10 points)
(5 points) a) Write the Boolean functions W,X,Y,Z(A,B,C,D) implemented
by the following PAL:
ANSWER: W = AB!C!D + !A!BC!D
ANSWER: X = A!B + BCD
ANSWER: Y = !AB + CD + A!B!D
ANSWER: Z = BW + A!C!D + !A!B!CD
= B(AB!C!D+!A!BC!D) + A!C!D + !A!B!CD (required function of A,B,C,D) = AB!C!D + A!C!D + !A!B!CD (simplified โ not required)
X
X
X
X
YOUR NAME:
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Question 3: Memory Circuits (10 points)
(3 points) a) Write down the 4-bit values (B3,B2,B1,B0) stored in each of
the four memory locations in this NAND FLASH ROM circuit, as addressed
by the four word line bits (W3,W2,W1,W0). Each bit is selected one at a
time to read out by setting the associated column address high.
Assume that each bit line is connected to a pullup resistor to the positive
power supply.
Transistors with charge on their floating gate are indicated with a * symbol.
Note: this is actually a NOR flash ROM, not a NAND ROM!
ANSWER: [W0]:__0111______
[W1]:__1010______
[W2]:__0101______
[W3]:__1010______
B3 B2 B1 B
W
W
W
W
YOUR NAME:
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(7 points) b) Draw a NOR ROM circuit that implements the CM3 and CM
functions of question 2b. Draw the address decoder (which takes in the 4
input signals and outputs the 16 word lines) as a block symbol. You do not
need to show how the address decoder is implemented.
YOUR NAME:
________________________________________________________________________
(7 marks) b) Write a complete VHDL design entity describing the circuit
shown below (a quadrature encoder for a rotary encoder). Assume that the
flipflops trigger on the rising edge of the CLK input (not shown). The inputs
to the circuit are the signals A, B, CLK, and the outputs are Ap, Bp, F_quad,
and Dir_err. Do not use components, just implement the functionality using
simple assignment statements and if statements in process blocks. Note that
the lower flipflop is a JK flipflop, while the others are D flipflops.
YOUR NAME:
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library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity Q4b is Port ( CLK : in STD_LOGIC; A : in STD_LOGIC; B : in STD_LOGIC; Ap : out STD_LOGIC; Bp : out STD_LOGIC; F_quad : out STD_LOGIC; Dir_err : out STD_LOGIC); end Q4b;
architecture ans of Q4b is
signal Adly, Bdly, Api, Bpi, J, K, Dir_erri : STD_LOGIC;
begin --do the combinational logic stuff outside the process Api <= A xor Adly; Bpi <= B xor Bdly; F_quad = Api and Bpi; J <= Api and (A xor B); K <= Bpi and (A xor B); Ap <= Api; Bp <= Bpi; -- note: we need to use internal signals -- Api and Bpi to copy Ap and Bp since VHDL does not allow -- output port signals to be on the RHS of assignment -- statements (which they would be in the assignment for -- F_quad) Dir_err <= Dir_err; -- note: we use an internal signal --for the output of the JK flipflop to allow toggling, --which needs to read the current value of the output
process(CLK) begin if rising_edge(CLK) then Adly <= A; -- implements the D flipflops Bdly <= B; if J = โ0โ then if K = โ1โ then Dir_erri <= โ0โ; -- reset end if; -- if K=0 we just hold the value else -- J = 1 if K = 0 then Dir_erri <= โ1โ; -- set else
