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Reg.no - 19BEC
Name- Tom Michael Shibu
Faculty-Prof. Prathiba
Experiment ‐03‐ Magnitude Comparator, Binary to Gray and Gray to
Binary Scaling Using Verilog HDL
1. Magnitude Comparator
Design
module mag_compare(output A_lt_B,A_eq_B,A_gt_B,input[3:0]A,B); assign A_lt_B=(A<B); assign A_gt_B=(A>B); assign A_eq_B=(A==B); endmodule
Test Bench
module magnitude_comparator_test(); reg [3:0]A; reg [3:0]B; wire A_lt_B,A_eq_B,A_gt_B; mag_compare uut( A_lt_B,A_eq_B,A_gt_B,A,B); initial begin $dumpfile("dump.vcd"); $dumpvars(1,A_lt_B); $dumpvars(1,A_eq_B); $dumpvars(1,A_gt_B); $dumpvars(1,A); $dumpvars(1,B); $monitor("A=%b, B=%b, A_lt_B=%b, A_eq_B=%b, A_gt_B=%b",A,B,A_lt_B,A_eq_B,A_gt_B); A=4'b0000; B=4'b0000; #20 A=4'b0011; B=4'b0001; #20 A=4'b0110; B=4'b1010; #20 A=4'b0111; B=4'b0101; End
VCD info: dumpfile dump.vcd opened for output. A=0000, B=0000, A_lt_B=0, A_eq_B=1, A_gt_B= A=0011, B=0001, A_lt_B=0, A_eq_B=0, A_gt_B= A=0110, B=1010, A_lt_B=1, A_eq_B=0, A_gt_B= A=0111, B=0101, A_lt_B=0, A_eq_B=0, A_gt_B= Finding VCD file... ./dump.vcd
2. Binary to Gray scale converter
Design
module binarytogray(output [3:0]out,input [3:0]A); assign out[0]=A[0]^A[1]; assign out[1]=A[1]^A[2]; assign out[2]=A[2]^A[3]; assign out[3]=A[3]; endmodule
Test Bench
module graytobinary_test(); reg [3:0]A; wire [3:0]out; binarytogray uut(out,A); initial begin $dumpfile("dump.vcd"); $dumpvars(1,A); $dumpvars(1,out); $monitor("A=%b,out=%b",A,out); A=4'b0010; #10 A=4'b1010; #10 A=4'b0111; end endmodule
VCD info: dumpfile dump.vcd opened for output. A=0011,out= A=0111,out= A=1010,out= Finding VCD file... ./dump.vcd
Result & Inference
What I learned from this experiment is how to code the magnitude comparator, binary to gray and gray to binary converter in verilog HDL, also to understand their output characteristics.
