Download CMOS LOGIC DESIGN 4e Solutions Manual and more Exercises Very large scale integration (VLSI) in PDF only on Docsity!
Solutions
Solutions for CMOS VLSI Design 4th Edition. Last updated 26 March 2010.
Chapter 1
1.1 Starting with 100,000,000 transistors in 2004 and doubling every 26 months for 12
years gives transistors. 1.2 See Figure 1.4 for data through 2009. Some data includes:
Table 1: Microprocessor transistor counts
Date CPU Transistors (millions)
3/22/93 Pentium 3. 10/1/95 Pentium Pro 5. 5/7/97 Pentium II 7. 2/26/99 Pentium III 9. 10/25/99 Pentium III 28 11/20/00 Pentium 4 42 8/27/01 Pentium 4 55 2/2/04 Pentium 4 HT 125
10 8 2
12 ⋅ 12 ⎝ --------------- 26 - ⎠ ⎛ ⎞
2 SOLUTIONS
The transistor counts double approximately every 24 months.
1.3 Let your imagination soar! 1.4 Don’t be a jerk! Your answers should vary.
1
10
100
1990 1995 2000 2005 Year
Transistors (Millions)
A B C D Y A B
Y
C
D
D
A B C
A B
C
D
D
A B C Y
A B
C
C
A B
B
A
A
B
(c)
Y
(a) (b)
4 SOLUTIONS
1.11 The minimum area is 5 tracks by 5 tracks (40 λ x 40 λ = 1600 λ^2 ). 1.12 The layout is 40 λ x 40 λ if minimum separation to adjacent metal is considered, exactly as the track count estimated.
A1A1A0 A
Y
Y
Y
Y
(a)
Y
Y
A
A
A
A
A
(b)
A
VDD
GND
B C
Y
D
CHAPTER 1 SOLUTIONS 5
1.14 6 tracks wide by 6 tracks tall, or 2304 λ^2.
1.15 This latch is nearly identical save that the inverter and transmission gate feedback has been replaced by a tristate feedaback gate.
n+ n+
p substrate
p+ p+
n well
A
Y VDD
n+
GND
B
D Y CLK
CLK
CLK
CLK
CHAPTER 2 SOLUTIONS 7
1.19 20 transistors, vs. 10 in 1.16(a).
(c) The area of this stick diagram is 11 x 6 tracks = 4224 λ^2 if the polysilicon can be bent.
1.21 The Electric lab solutions are available to instructors on the web. The Cadence labs include walking you through the steps.
Chapter 2
A
Y
B A C B C
G
G
G
G
P
P
P
G
G2 P
G1 P
G0 P
G
(a)
VDD
GND
G0 P1 G1 P2 G2 P3 G
(b)
G
8 SOLUTIONS
2.2 In (a), the transistor sees Vgs = V (^) DD and Vds = V (^) DS. The current is
In (b), the bottom transistor sees V (^) gs = V (^) DD and V (^) ds = V 1. The top transistor sees V (^) gs = VDD - V 1 and V (^) ds = V (^) DS - V 1. The currents are
Solving for V 1 , we find
Substituting V 1 indo the I (^) DS 2 equation and simplifying gives I (^) DS 1 = IDS 2. 2.3 The body effect does not change (a) because Vsb = 0. The body effect raises the threshold of the top transistor in (b) because V (^) sb > 0. This lowers the current through the series transistors, so IDS 1 > IDS 2. 2.4 C permicron = ε L / tox = 3.9 * 8.85e-14 F/cm * 90e-7 cm / 16e-4 μm= 1.94 fF/μm.
( )
14 2 8
ox
W W W
C A V
L L L
β μ μ
− −
⎝ ⋅^ ⎠⎝^ ⎠
0 1 2 3 4 5
0
1
2
V (^) ds
I^ ds
(mA)
V (^) gs = 5
V (^) gs = 4
Vgs = 3
V (^) gs = 2 V (^) gs = 1
1
DS DS DD t DS
V
I V V V
β (^) ⎛ ⎞
( )
( ) ( ) 1 1 2 1 1 1
DS DS DD t DD t DS
V V^ V
I β V V V β V V V V V
⎛ ⎞ ⎛^ − ⎞
( ) ( )
2 1
DS DD t DD t DD t DS
V
V V V V V V V V
10 SOLUTIONS
2.11 The nMOS will be OFF and will see V (^) ds = V (^) DD , so its leakage is
2.12 If the voltage at the intermediate node is x , by KCL:
Now, solve for x using n = 1:
Substituting, the current is exactly half that of the inverter. 2.13 Assume V (^) DD = 1.8 V. For a single transistor with n = 1.4,
For two transistors in series, the intermediate voltage x and leakage current are found as:
In summary, accounting for DIBL leads to more overall leakage in both cases. However, the leakage through series transistors is much less than half of that through a single transistor because the bottom transistor sees a small Vds and much less DIBL. This is called the stack effect. For n = 1.0, the leakage currents through a single transistor and pair of transistors are 13.5 pA and 0.9 pA, respectively.
21 .8 (^69)
t T
V nv I I veeleak dsn β T pA
− = = =
I leak βv T
2
e
e
- V (^) t nv-------- (^) T-
1 e
βv T
2
e
e
- ( x +V (^) t) ----------------------nv (^) T -
1 T^ T ln
x x v nv e e x vT
⎛ −^ ⎞ − ⎜ −^ ⎟=^ →= ⎜ ⎟ ⎝ ⎠
t DD T
V V nv
I leak I dsn v eT e pA
η β
− +
( )
( )
69 mV; 69 pA
t^ DD^ t T T T
t DD^ t T T T
V x x V x V x nv v nv leak T T
V x x V^ x^ V^ x nv v nv
leak
I v e e e v e e
e e e
x I
η η
η η
β β
− + − − − −
− + − −^ −^ −
⎜ −^ ⎟=
CHAPTER 2 SOLUTIONS 11
The graph below is normalized to V (^) DD = 1, β = 2, and V (^) t = V (^) DD /5. This is a bad buffer because the output does not swing rail-to-rail and because it exhibits hystere- sis.
( )
( )
2 2
2 2
t dsn t t
t dsp t t
A Y V
I
A Y V A Y V
A Y V
I
A Y V A Y V
β
β
⎧⎪ −^ <
⎪⎩ −^ −^ −^ >
⎧⎪^ −^ > −
⎪⎩ −^ −^ −^ < −
( )
( )
2 2
2 2
t dsn t t
t dsp t t
A Y V
I
A Y V A Y V
A Y V
I
A Y V A Y V
β
β
⎧⎪ −^ <
⎪⎩ −^ −^ −^ >
⎧⎪^ −^ > −
⎪⎩ −^ +^ −^ < −
CHAPTER 2 SOLUTIONS 13
In region B, the nMOS is saturated and pMOS is linear:
In region D, the nMOS is linear and the pMOS is saturated:
2.17 Either take the grungy derivative for the unity gain point or solve numerically for V (^) IL = 0.46 V, VIH = 0.54 V, VOL = 0.04 V, VOH = 0.96 V, NM (^) H = NM (^) L = 0.42 V.
2.18 The switching point where both transistors are saturated (region C) is found by solv- ing for equal currents:
The output voltage in region B is found by solving
( ) ( )
( ) ( )
( ) ( ) ( ) ( )
(^2) out in in out
2 2 out in in in in
DD t DD t DD
t t t DD DD t
V V
V V V V V V V
V V V V V V V V V V V
β β
( ) ( )
( ) ( ) ( )
(^2) out in in out
2 2 out in in in
DD t t
t t DD t
V
V V V V V V
V V V V V V V V
β β
( ) (^) ( )
( ) ( ( )) (^) ( ( ))
( ) ( )
2 2 in in
2 2 2 in in
in
n^ p tn DD tp
n p n tn p DD tp n tn p DD tp
n tn p DD tp DD tp tn n p
n p
n DD tp tn p
n p
V V V V V
V V V V V V V V
V V V V V V
V
V V V
β^ β
β β β β β β
β β β β
β β
β β
β β
( ) ( )
( ) ( )
( ) ( ) (^ )^ ( )
(^2) out in in out
(^2 ) out in in in in
np 2 2
n DD tn p DD tp DD
tp tp tn DD DD tp
V V
V V V V V V V
V V V V V V V V V V V
β β
β β
14 SOLUTIONS
and the output voltage in region D is
2.19 Take derivatives or solve numerically for the unity gain points: VIL = 0.43 V, V (^) IH = 0.50 V, VOL = 0.04 V, VOH = 0.97 V, NM (^) H = 0.39, NM (^) L = 0.47 V. 2.20 (a) 0; (b) 2| V (^) tp |; (c) | V (^) tp |; (d) V (^) DD - V (^) tn 2.21 (a) 0; (b) 0.6; (c) 0.8; (d) 0.
Chapter 3
3.1 First, the cost per wafer for each step and scan. 248nm – number of wafers for four years = 43652480 = 2,803,200. 193nm = 43652420 = 700,800. The cost per wafer is the (equipment cost)/(number of wafers) which is for 248nm $10M/ 2,803,200 = $3.56 and for 193nm is $40M/700,800 = $57.08. For a run through the equipment 10 times per completed wafer is $35.60 and $570.77 respectively. Now for gross die per wafer. For a 300mm diameter wafer the area is roughly 70,650 mm 2 (π( r^2 / A – r /(sqrt(2 A ))). For a 50mm^2 die in 90nm, there are 1366 gross die per wafer. Now for the tricky part (which was unspecified in the question and could cause confusion). What is the area of the 50nm chip? The area of the core will shrink by (90/50) 2 = .3086. The best case is if the whole die shrinks by this fac- tor. The shrunk die size is 50*.3086 = 15.43mm 2. This yields 4495 gross die per wafer. The cost per chip is $35.60/1413 = $0.026 and $570.77/4578 = $0.127 respectively for 90nm and 50nm. So roughly speaking, it costs $0.10 per chip more at the 50nm node. Obviously, there can be variations here. Another way of estimating the reduced die size is to estimate the pad area (if it’s not specified as in this exercise) and take that out or the equation for the shrunk die size. A 50mm^2 chip is roughly 7mm on a side (assuming a square die). The I/O pad ring can be (approximately) between 0.5 and 1 mm per side. So the core area might range from 25mm 2 to 36mm 2. When shrunk, this core area might vary from 7.7 to 11.1mm 2 (2.77 and 3.33mm on a side respec- tively). Adding the pads back in (they don’t scale very much), we get die sizes of 4.77 and 4.33 mm on a side. This yield possible areas of 18.7 to 22.8 mm 2 , which in turn yields a cost of processing on the stepper of between $0.155 and $0.189. This is a rather more pessimistic (but realistic) value.
( ) (^ )
( ) ( ) (^) ( )
(^2) out in in out
2 2 out in in in
p n
p DD tp n tn
tn tn DD tp
V
V V V V V V
V V V V V V V V
β β
β β
16 SOLUTIONS
3.8 The vertical pitch is divided into three basic segments. First, we have to determine the spacing of the n-transistor to the GND bus. The next segment is defined by the n-transistor to p-transistor spacing. Finally, the p-transistor to VDD bus spacing needs to be determined. (all spacings are center to center). N-transistor to GND bus First let us assume minimum metal1 widths. Next, the width of a metal contact is equal to the contact width plus twice the overlap of the metal over the contact = 2 + 21 = 4 λ. The minimum width of a transistor is the contact width plus 2active overlap of contact = 2 + 21 = 4 λ (actually the same as a metal1 contact). So the spacing of the n-transistor to the GND bus will be half the GND bus width plus metal spacing plus half of the metal contact width = 0.53 + 3 + 0.54 = 6.5 λ. N-transistor to P-transistor spacing There are two cases: with a polysilicon contact to the gate and without. With the metal-to-polysilicon contact, the spacing will probably be half of the n-transistor width plus the metal space plus the polysilicon contact width plus the metal space plus half the p-transistor width = 0.54 + 3 + 4 + 3 + 0.54 = 14 λ. The spacing without a contact is half the n-transistor width plus n-active to p-active spacing plus half the p-transistor width = 0.54 + 4 + 0.54 = 8 λ. However, the n-well must sur- round the pMOS transistor by 6 and be 6 away from the nMOS. This sets a mini- mum pitch of 0.54 + 6 + 6 + 0.54 = 16 for both cases. P-transistor to VDD bus By symmetry, this is also 6.5 λ. Summary The total pitch is 26.5 + 16 = 29 λ. The total height of the inverter is 35 λ including the complete supply lines and spacing to an adjacent cell. In the case where the V (^) DD and GND busses are not minimum pitch, the vertical pitch and cell height increase appropriately. In this inverter the substrate connections have not been included. They could be included in the horizontal plane so that the vertical pitch is not affected. If they are included under the metal power busses, the spacing on the transistors to the power busses may be altered. Normally, this is what is done the power bus can be sized up to account for the spacing. This helps power distribution and does not affect the pitch much. In an SOI process, if the n to p spacing is 2 λ rather than 12 λ, the pitches are 2*6.
- 14 = 27 λ and 2 * 6.5 + 6 = 19 λ respectively for interior poly connection and not. In older standard cell families (two and three level metal processes), the polysilicon contact was often eliminated and the contact to the gate was made above or below the cell in the routing channels. With modern standard cells, all connections to the cells are normally completed within the cell (up to metal2).
CHAPTER 4 SOLUTIONS 17
3.9 A fuse is a necked down segment of metal (Figure 3.24) that is designed to blow at a certain current density. We would normally set the width of the fuse to the minimum metal width – is this case 0.5 μm. At this width, the maximum current density is 500 μA. At a programming current of 10 times this – 5mA, the fuse should blow reli- ably. The “fat” conductor connecting to the fuse has to be at least 2.5 μm to carry the fuse current. Actually, the complete resistance from the programming source to the fuse has to be calculated to ensure that the fuse is the where the maximum voltage drop occurs. The length of the fuse segment should be between 1 and 2 μm. Why? It’s a guess – in a real design, this would be prototyped at various lengths and the reliability of blowing the fuse could be determined for different lengths and different fuse cur- rents. The fabrication vendor may be able to provide process-specific guidelines. One needs enough length to prevent any sputtered metal from bridging the thicker conductors.
Chapter 4
4.1 The rising delay is (R/2)8C + R(6C+5hC) = (10+5h)RC if both of the series pMOS transistors have their own contacted diffusion at the intermediate node. More realisitically, the diffusion will be shared, reducing the delay to (R/2)4C + R(6C+5hC) = (8+5h)RC. Neglecting the diffusion capacitance not on the path from Y to GND, the falling delay is R*(6C+5hC) = (6+5h)RC.
4.2 The rising delay is (R/2)2C + R(5C+5hC) = (6+5h)RC and the falling delay is R*(5C+5hC) = (5+5h)RC.
4.3 The rising delay is (R/2)(8C) + (R)(4C + 2C) = 10 RC and the falling delay is (R/ 2)*(C) + R(2C + 4C) = 6.5 RC. Note that these are only the parasitic delays; a real
A B Y 1 1
4
4
VDD A
GND
B
Y
2C 4C
C
4 4
1 1
CHAPTER 4 SOLUTIONS 19
4.8 (a) 4 units. (b) (3/4 units).
4.9 g = 6/3 is the ratio of the input capacitance (4+2) to that of a unit inverter (2 + 1).
4.10 (a) should be faster than (b) because the NAND has the same parasitic delay but lower logical effort than the NOR. In each design, H = 6, B = 1, P = 1 + 2 = 3. For (a), G = (4/3) * 1 = (4/3). F = GBH = 8. f = 81/2^ = 2.8. D = 2 f + P = 8.6 τ. x = 6C * 1 / f = 2.14C. For (b), G = 1 *(5/3). F = GBH = 10. f = 10 1/2^ = 3.2. D = 2 f + P = 9.3 τ. x = 6C * (5/3) / f = 3.16C.
4.11 D = N ( GH )1/ N^ + P. Compare in a spreadsheet. Design (b) is fastest for H = 1 or 5. Design (d) is fastest for H = 20 because it has a lower logical effort and more stages to drive the large path effort. (c) is always worse than (b) because it has greater log- ical effort, all else being equal.
4.12 H = (64 * 3) / 10 = 19.2. B = 32 / 2 = 16. Compare several designs in a spreadsheet. The five-stage design is fastest, with a path effort of F = GBH = 683 and stage effort of f = F 1/5^ = 3.69. The gate sizes from end to start are: 192 * 1 / 3.69 = 52; 52 * (4/
- / 3.69 = 18.8; 18.8 * 1 / 3.69 = 5.1; 5.1 * (5/3) / 3.69 = 2.3; 2.3 * 1 / 3.69 = 0.625.
Comparison of 6-input AND gates
Design G P N D ( H =1) D ( H =5) D ( H =20)
(a) 8/3 * 1 6 + 1 2 10.3 14.3 21.
(b) 5/3 * 5/3 3 + 2 2 8.3 12.5 19.
(c) 4/3 * 7/3 2 + 3 2 8.5 12.9 20.
(d) 5/3 * 1 * 4/3 * 1 3 + 1 + 2 + 1 4 11.8 14.3 17.
Comparison of decoders
Design G P N D
NAND5 + INV 7/3 6 2 59.
A B
Y
C D
4 4 4 4
2 2 2 2
20 SOLUTIONS
4.13 One reasonable design consists of XNOR functions to check bitwise equality, a 16- input AND to check equality of the input words, and an AND gate to choose Y or 0. Assuming an XOR gate has g = p = 4, the circuit has G = 4 * (9/3) * (6/3) * (5/3) =
- Neglecting the branch on A that could be buffered if necessary, the path has B = 16 driving the final ANDs. H = 10/10 = 1. F = GBH = 640. N = 4. f = 5.03, high but not unreasonable (perhaps a five stage design would be better). P = 4 + 4 + 4 + 2 = 14. D = Nf + P = 34.12 τ = 6.8 FO4 delays. z = 10 * (5/3) / 5.03 = 3.3; y = 16 * z * (6/3) / 5.03 = 21.1; x = y * (9/3) / 5.03 = 12.6.
4.14 tpd = 76 ps, 72 ps, 67 ps, 70 ps for the XL, X1, X2, and X4 NAND2 gates, respec- tively. The XL gate has slightly higher parasitic delay because the wiring capaci- tance is a greater fraction of the total. It also has a slightly higher logical effort, possibly because stray wire capacitance is counted in the input capacitance and forms a greater fraction of the total C in. 4.15 Using average values of the intrinsic delay and K load , we find d abs = (0.029 + 4.55* C load) ns. Substituting h = C load / C in , this becomes d abs = (0.029 + 0.020 h ) ns. Normalizing by τ, d = 1.65 h + 2.42. Thus the average logical effort is 1.65 and par- asitic delay is 2.42. 4.16 X2: g = 1.55; p = 2.14. X4: g = 1.56; p = 2.17. The logical efforts are about 6% lower and parasitic delay 12% lower than in the X1 gate. Because of differing lay-
INV + NAND5 + INV 7/3 7 3 33.
NAND3 + INV + NAND2 + INV 20/9 7 4 27.
INV + NAND3 + INV + NAND2 + INV 20/9 8 5 26.
**NAND3 + INV + NAND2 + INV
20/9 9 6 26.
NAND2 + INV + NAND2 + INV + NAND2 + INV 64/27 9 6 27.
Comparison of decoders
Design G P N D
A[0]
B[0]
A[15]
B[15] (^) Y[15]
10 Y[0]
x y
z
