Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Community
Ask the community for help and clear up your study doubts
Discover the best universities in your country according to Docsity users
Free resources
Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors
Course: Microelectronics Circuit Professer: Truong Cong Dung Nghi
Typology: Slides
1 / 13
This page cannot be seen from the preview
Don't miss anything!
Trương Công Dung Nghi
Operational amplifier (op-amp): integrated circuit that amplifies the
difference between two input voltages and produces a single output.
‣ Two input terminals: inverting input terminal (-) and non-inverting input
terminal (+)
‣ One output terminal
‣
Two dc power supplies V+ and V-
‣ Other terminal for offset nulling.
2
Inverting
input
Non-inverting
input
Output
Trương Công Dung Nghi
Ideal characteristics of op-amp
= i 2
= 0 (regardless of the input voltage)
= A(v 2
) (regardless of the load)
Infinite common-mode rejection
Infinite bandwidth
3
626 Part 2 Analog Electronics
od
2
1
O
1
2
o
Practical Specifications
A
od
(v
2
1
)
A
od
≅ ∞
R
o
≈ 0
i
1
≅ 0
i
2
≅ 0
v
1
v
0
v
2
Figure 9.6 Parameters of the ideal op-amp
644_ch09_619-686.qxd 6/19/09 4:25 AM Page 626 pmath DATA-DISK:Desktop Folder
Trương Công Dung Nghi
Differential and Common-Mode Signals
Differential input signal:
Common-mode input signal:
4
v
id
= v
2
v
1
v
icm
(v
1
2
2.1.3 Differential and Common-Mode Signa
The differential input signal v
Id
is simply the difference be
v
1
and v
2
; that is,
The common-mode input signal v
Icm
is the average of the
namely,
Equations (2.1) and (2.2) can be used to express the input sign
differential and common-mode components as follows:
and
These equations can in turn lead to the pictorial representation
Figure 2.4 Representation of the signal sources v
1
and v
2
in terms of th
components.
v
Id
v
2
v
1
v
Icm
1
2
v
1
v
2
v
1
v
Icm
v
Id
v
2
v
Icm
v
Id
!
"
v
1
1
!
"
v
2
2
"
!
v
Id
"
!
1
2
!
"
v
Icm
v
Id
Trương Công Dung Nghi
Closed-loop gain: 7 The points just made are more clearly illustrated by deriving an expression for the closed- loop gain under the assumption that the op-amp open-loop gain A is finite. Figure 2.7 shows the analysis. If we denote the output voltage v O , then the voltage between the two input terminals of the op amp will be Since the positive input terminal is grounded, the voltage at the negative input terminal must be The current i 1 through R 1 can now be found from The infinite input impedance of the op amp forces the current i 1 to flow entirely through
2
. The output voltage v
O can thus be determined from Collecting terms, the closed-loop gain G is found as
We note that as A approaches ∞, G approaches the ideal value of Also, from Fig. 2. we see that as A approaches ∞, the voltage at the inverting input terminal approaches zero. This is the virtual-ground assumption we used in our earlier analysis when the op amp was
O
v
O
1
I
O
1
v
I
O
R
1
Figure 2.7 Analysis of the inverting configuration taking into account the finite open-loop gain of the op amp.
O
O
1
2
v
O
= – v
I
O
R
1
2
v
O
I
≡ R
2
1
2
1
=
2
1
The infinite input impedance of the op amp forces the current i 1 to flow enti R 2
. The output voltage v
O can thus be determined from Collecting terms, the closed-loop gain G is found as We note that as A approaches ∞, G approaches the ideal value of Also, we see that as A approaches ∞, the voltage at the inverting input terminal app This is the virtual-ground assumption we used in our earlier analysis when the Figure 2.7 Analysis of th configuration taking into accou open-loop gain of the op amp. v O v O
1
2
v O
= – -----
v I v O
R
1
© ¹ § · – R
2
v O v I
≡ R
2
1
1 1 R
2
1
= – R
2
1
finite input impedance of the op amp forces the current i 1 to flow entirely through e output voltage v O can thus be determined from ting terms, the closed-loop gain G is found as (2.5) te that as A approaches ∞, G approaches the ideal value of Also, from Fig. 2. e that as A approaches ∞, the voltage at the inverting input terminal approaches zero. s the virtual-ground assumption we used in our earlier analysis when the op amp was i 1 R 1
R 1
= = Figure 2.7 Analysis of the inverting configuration taking into account the finite open-loop gain of the op amp. v O v O A
1 R 2 = – v O A
= – v I v O
© ¹ § ·
2 G v O v I
≡ R 2 R 1
1 1 R 2 R 1 +( + ⁄ ) ⁄ A
=
2 R 1 ⁄. Trương Công Dung Nghi
Superposition theorem: ‣ determine the output voltage due to each input acting alone. ‣ sum these terms to determine the total output. 8 Part 2 Analog Electronics 9.3 SUMMING AMPLIFIER Objective: • Analyze and understand the characteristics of the summing operational amplifier. To analyze the op-amp circuit shown in Figure 9.14(a), we will use the superposition theorem and the concept of virtual ground. Using the superposition theorem, we will determine the output voltage due to each input acting alone. We will then alge- braically sum these terms to determine the total output.
R 1 R F R 2 R 3
R 1 R F R 2 R 3 (a) (b) i 4 v 1 = 0 v O v I 1 i 1 v I 2 i 2 v I 3 i 3 0 v O v I 1 i 2 = 0 i 3 = 0 v I 3 = 0 v I 2 = 0 0 i 1 = v I 1 R 1 Virtual ground
Figure 9.14 (a) Summing op-amp amplifier circuit and (b) currents and voltages in the summing amplifier If we set v I 2 = v I 3 = 0 , the current i 1 is i 1 = v I 1 R (9.24) 86.qxd 6/19/09 4:25 AM Page 636 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-09: Part 2 Analog Electronics 9.3 SUMMING AMPLIFIER Objective: • Analyze and understand the characteristics of the summing operational amplifier. To analyze the op-amp circuit shown in Figure 9.14(a), we will use the superposition theorem and the concept of virtual ground. Using the superposition theorem, we will determine the output voltage due to each input acting alone. We will then alge- braically sum these terms to determine the total output.
R 1 R F R 2 R 3
R 1 R F R 2 R 3 (a) (b) i 4 v 1 = 0 v O v I 1 i 1 v I 2 i 2 v I 3 i 3 0 v O v I 1 i 2 = 0 i 3 = 0 v I 3 = 0 v I 2 = 0 0 i 1 = v I 1 R 1 Virtual ground
Figure 9.14 (a) Summing op-amp amplifier circuit and (b) currents and voltages in the summing amplifier If we set v I 2 = v I 3 = 0 , the current i 1 is i 1 = v I 1 (9.24) 86.qxd 6/19/09 4:25 AM Page 636 pmath DATA-DISK:Desktop Folder:18.6.09:MHDQ134-09: v O 1 = R F R 1 v I 1 v O 2 = R F R 2 v I 2 v O 3 = R F R 3 v I 3 9
=
; ) v O = ✓ R F R 1 v I 1
R F R 2 v I 2
R F R 3 v I 3 ◆
Trương Công Dung Nghi
=> The output is in phase with the input.
9
Cha
1
2
1
2
1
2
1
I
1
1
1
1
I
1
2
2
1
O
2
I
O
2
1
2
I
1
I
O
2
v
O
I
2
1
I
1
2
R
1
R
2
i
2
v
O
v
I
i
1
v
1
v
2
Figure 9.15 Noninverting op-amp circuit
i
1
v
I
1
i
2
v
I
v
O
2
i
1
= i
2
v
I
1
v
I
v
O
2
v
v
O
v
I
2
1
Trương Công Dung Nghi
Voltage follower: unity-gain buffer
based on non-inverting configuration.
regardless of source and load:
v
= v O
/ v I
It is typically used as a buffer
amplifier to connect a source with
a high impedance to a low-impedance
load.
10
640 Part 2 Analog Electronics
Th
might s
other te
input im
for exam
serted b
buffer b
Co
1 k! lo
source
conside
of outpu
v
O
v
I
v
O
v
I
Figure 9.17 Voltage-
follower op-amp
nea80644_ch09_619-686.qxd 6/19/09 4:
Trương Công Dung Nghi
Single Op-Amp Difference Amplifier
13
2.4 Difference
(i.e., the resistance seen by v
Id
), called the differential input resistance R
id
, consider Fig. 2.19.
Here we have assumed that the resistors are selected so that
and
Now
Since the two input terminals of the op amp track each other in potential, we may write a
loop equation and obtain
Thus,
Note that if the amplifier is required to have a large differential gain , then R
1
of
necessity will be relatively small and the input resistance will be correspondingly low, a
drawback of this circuit. Another drawback of the circuit is that it is not easy to vary the dif-
ferential gain of the amplifier. Both of these drawbacks are overcome in the instrumentation
amplifier discussed next.
Figure 2.18 Analysis of the difference amplifier to determine its common-mode gain
v
O
i
1
R
2
R
4
R
1
R
3
i
2
!
"
v
Icm
v
Icm
! "
R
4
R
4
! R
3
"
!
A
cm
v
O
v
Icm
≡ ⁄.
3
1
4
2
id
Id
I
Id
1
I
1
I
id
1
2
1
i
1
= v
lcm
3
3
4
1
v
o
= v
lcm
4
3
4
3
4
2
1
cm
4
3
4
3
4
2
1
Trương Công Dung Nghi
Single Op-Amp Difference Amplifier
Ideal difference amplifier:
‣ Select R 3
and R 4
as: R 3
= R 1
and R 4
= R 2
⇒ Amplify the difference between the two input signals and reject common-
mode signals
14
) v
O
=
R
2
R
1
(v
I 2
v
I 1
) =
R
2
R
1
v
Id
) A
d
=
R
2
R
1
A
cm
=
R
4
R
3
4
✓
1
R
3
R
4
R
2
R
1
◆
Trương Công Dung Nghi
v n
(t): interference signal (approximately the same
at both leads)
15
544 Chapter 12 Operational Amplifiers
Lead 2
v
2
+
-
Electrodes
Lead 1
v
1
+
-
Figure 12.11 Two-lead
electrocardiogram
0
v
1
v
2
(V)
0
1
2
3
4
5
6
7
Figure
_
~
_
~
v
n
( t )
Equivalent
circuit for
lead 2
Lead 1
v 2
Lead 2
Equivalent
circuit for
lead 1
EKG ampli
v
n
( t )
v 1
R 1
R 1
R
2
Figure 12.13 EKG amplifier
Lead 2:
v
2
(t) + v
n
(t) = v
2
(t) + V
n
cos ( 377 t + φ
n
The interference signal, V
n
cos ( 377 t + φ
n
), is ap
both leads, because the electrodes are chosen to b
the same lead lengths) and are in close proximity
nature of the interference signal is such that it is c
it is a property of the environment the EKG instr
the basis of the analysis presented earlier, then,
v
out
=
R
2
R
1
[(v
1
n
(t)) − (v
2
n
(t))]
or
v
out
=
R
2
R
1
(v
1
− v
2
)
544 Chapter 12 Operational Amplifiers
Lead 2
v 2
+
-
Electrodes
Lead 1
v
1
+
-
Figure 12.11 Two-lead
electrocardiogram
0 0.2 0.
Time (s)
v
1
v
2
(V)
0.6 0.
0
1
2
3
4
5
6
7
Figure 12.12 EKG waveform
_
~
_
~
v n
( t )
Equivalent
circuit for
lead 2
Lead 1
v 2
Lead 2
Equivalent
circuit for
lead 1
V
out
EKG amplifier
v n
( t )
v 1
R 1
R 1
R 2
R 2
Figure 12.13 EKG amplifier
Lead 2:
v
2
(t) + v
n
(t) = v
2
(t) + V
n
cos ( 377 t + φ
n
)
The interference signal, V n
cos ( 377 t + φ n
), is approximately the same at
both leads, because the electrodes are chosen to be identical (e.g., they have
the same lead lengths) and are in close proximity to each other. Further, the
nature of the interference signal is such that it is common to both leads, since
it is a property of the environment the EKG instrument is embedded in. On
v
1 / 2
(t) + v
n
(t) = v
1 / 2
(t) + V
n
cos (377t +
n
v 2
+
-
Electrodes
v
1
+
-
Figure 12.11 Two-lead
electrocardiogram
0 0.2 0.
Time (s)
v
1
v
2
(V)
0.6 0.
0
1
2
3
4
5
6
Figure 12.12 EKG waveform
_
~
_
~
v n
( t )
Equivalent
circuit for
lead 2
Lead 1
v
2
Lead 2
Equivalent
circuit for
lead 1
V out
EKG amplifier
v
n
( t )
v 1
R 1
R 1
R 2
R 2
Figure 12.13 EKG amplifier
Lead 2:
v 2
(t) + v n
(t) = v 2
(t) + V n
cos ( 377 t + φ n
)
The interference signal, V n
cos ( 377 t + φ
n
), is approximately the same at
both leads, because the electrodes are chosen to be identical (e.g., they have
the same lead lengths) and are in close proximity to each other. Further, the
nature of the interference signal is such that it is common to both leads, since
it is a property of the environment the EKG instrument is embedded in. On
the basis of the analysis presented earlier, then,
v
out
=
R
2
R
1
[(v
1
n
(t)) − (v
2
n
(t))]
or
v
out
=
R
2
R
1
(v
1
− v
2
)
Thus, the differential amplifier nullifies the effect of the 60-Hz interference,
while amplifying the desired EKG waveform.
ECG Amplifier
v
out
=
R
2
R
1
(v
1
v
2
)
Trương Công Dung Nghi
Differential input resistance:
‣
large differential gain (R 2
/R 1
)
⇒ R 1
of necessity will be relatively small
⇒ input resistance will be low
16
(i.e., the resistance seen by v
Id
), called the differential input resis
Here we have assumed that the resistors are selected so that
and
Now
Since the two input terminals of the op amp track each other i
loop equation and obtain
Thus,
Note that if the amplifier is required to have a large differentia
necessity will be relatively small and the input resistance wil
drawback of this circuit. Another drawback of the circuit is that
ferential gain of the amplifier. Both of these drawbacks are over
amplifier discussed next.
Figure 2.18 Analysis of the difference amplifier to determine its commo
v
O
R
4
R
3
!
"
v
Icm
v
Icm
R
4
R
4
! R
3
!
3
1
4
id
v
Id
i
I
v
Id
1
i
I
1
i
I
= + +
id
1
=
v
Id
R
id
I
I
Figure 2
tance of t
the case R
(i.e., the resistance seen by v
Id
), called the differential input resistance R
id
, co
Here we have assumed that the resistors are selected so that
and
Now
Since the two input terminals of the op amp track each other in potential,
loop equation and obtain
Thus,
Note that if the amplifier is required to have a large differential gain
necessity will be relatively small and the input resistance will be correspo
drawback of this circuit. Another drawback of the circuit is that it is not easy
ferential gain of the amplifier. Both of these drawbacks are overcome in the
amplifier discussed next.
Figure 2.18 Analysis of the difference amplifier to determine its common-mode gain
v
O
i
1
R
2
R
4
R
1
R
3
i
2
!
"
v
Icm
v
Icm
R
4
R
4
! R
3
"
!
A
3
1
4
2
id
v
Id
i
I
v
Id
1
i
I
1
i
I
= + +
id
1
=
2
v
Id
R
id
I
I
Figure 2.19 Finding th
tance of the difference
the case R
3
= R
1
and R
4
=
v
Id
= R
1
i
i
1
i
i
) R
id
⌘
v
Id
i
i
= 2R
1
Trương Công Dung Nghi
19
Chapter 9 Ideal Operational Am
supply voltage is reached. In many applications, a transistor switch needs to b
in parallel with the capacitor to periodically set the capacitor voltage to zero
The second generalized inverting op-amp uses a capacitor for Z
1
and a
for Z
2
, as shown in Figure 9.31. The impedances are Z
1
= 1 / sC
1
and Z
2
=
the voltage transfer function is
v
O
v
I
= −
Z
2
Z
1
= − s R
2
C
1
(
The output voltage is
v
O
= − s R
2
C
1
v
I
(
Equation (9.71(b)) represents differentiation in the time domain, as foll
v
O
( t ) = − R
2
C
1
d v
I
( t )
dt
The circuit in Figure 9.31 is therefore a differentiator.
Differentiator circuits are more susceptible to noise than are the integr
cuits. Input noise fluctuations of small amplitudes may have large derivative
differentiated, these noise fluctuations may generate large noise signals at the
creating a poor output signal to noise ratio. This problem may be alleviated
ing a resistor in series with the input capacitor. This modified circuit then di
ates low-frequency signals but has a constant high-frequency gain.
EXAMPLE 9.
R
2
C
1
v
O
v
I
a80644_ch09_619-686.qxd 6/19/09 4:25 AM Page 653 pmath DATA-DISK:Desk
2
O
I
2
1
2
1
O
2
1
I
O
2
1
I
EXAMPLE 9.
o
1
2
t
0
′
1
2
′
t
0
1
2
O
− 3
1
2
1
2
2
Figure 9.31 Op-amp differentiator
Output voltage:
v
O
= sR
2
1
v
I
or v
O
(t) = R
2
1
dv
I
(t)
dt
Trương Công Dung Nghi
Zero-Level Detection:
‣
High open-loop voltage gain ⇒ very small difference voltage between the
two inputs drives the amplifier into saturation
20
C
Nonzero-Level Detection
The zero-level detector in Figure 13–1 can be modified to detect positive and negative volt-
ages by connecting a fixed reference voltage source to the inverting (-)input, as shown in
V
out
V
in
(a) (b)
V
in
0
V
out
0
out ( max )
out ( max )
t
t
! FIGURE
The op-amp
o-Level Detection
V
out
V
in
(a) (b)
V
in
0
V
out
0
out ( max )
out ( max )
t
t
! FIGU
The op-a
Trương Công Dung Nghi
21
Nonzero-Level Detection
The zero-level detector in Figure 13–1 can be modified to detect positive and negative volt-
ages by connecting a fixed reference voltage source to the inverting input, as shown in
Figure 13–2(a). A more practical arrangement is shown in Figure 13–2(b) using a voltage
divider to set the reference voltage, V REF
, as follows:
where + V is the positive op-amp dc supply voltage. The circuit in Figure 13–2(c) uses a
V
REF
=
R
2
R
1
2
(+ V )
(-)
(a) (b)
V
out
V
in
(a) Battery reference
V REF
V
out
V
in
(c) Zener diode sets reference voltage
R
V
Z
V
out
V
in
(b) Voltage-divider reference
V
REF
R
1
R
2
(d) Waveforms
V
in
0
V
out
out ( max )
out ( max )
V
REF
0
t
t
" FIGURE 13–
Nonzero-level detectors.
zener diode to set the reference voltage ( V REF
! V
Z
). As long as V
in
is less than V
REF
, the
Trương Công Dung Nghi
Nonzero-Level Detection:
22
COMPARATOR
Nonzero-Level Detection
The zero-level detector in Figure 13–1 can be modified to detect positive and negative volt-
ages by connecting a fixed reference voltage source to the inverting input, as shown in
Figure 13–2(a). A more practical arrangement is shown in Figure 13–2(b) using a voltage
divider to set the reference voltage, V
REF
, as follows:
where + V is the positive op-amp dc supply voltage. The circuit in Figure 13–2(c) uses a
V
REF
=
R
2
R
1
2
(+ V )
(-)
V
out
V
in
(a) (b)
V
in
0
V
out
0
out ( max )
out ( max )
t
t
! FIGURE 13–
The op-amp as a zero-lev
V
out
V
in
(a) Battery reference
V
REF
V
V
in
(c) Zener diode sets reference voltage
R
V
Z
V
out
V
in
(b) Voltage-divider reference
V
REF
R
1
R
2
V
in
0
out ( max )
V
REF
t
zener diode to set the reference voltage ( V
REF
! V
Z
). As long as V
in
is less than V
REF
, the
The zero-level detector in Figure 13–1 can be modified to detect positive and negative volt-
ages by connecting a fixed reference voltage source to the inverting input, as shown in
Figure 13–2(a). A more practical arrangement is shown in Figure 13–2(b) using a voltage
divider to set the reference voltage, V
REF
, as follows:
where + V is the positive op-amp dc supply voltage. The circuit in Figure 13–2(c) uses a
V
REF
=
R
2
R
1
2
(+ V )
(-)
V
out
V
in
(a) (b)
V
in
0
V
out
0
out ( max )
out ( max )
t
t
The op-
V
out
V
in
(a) Battery reference
V
REF
V
in
(c) Zener diode sets re
R
V
Z
V
out
V
in
(b) Voltage-divider reference
V
REF
R
1
R
2
(d) Waveforms
V
in
0
V
out
out ( max )
out ( max )
V
REF
0
t
t
" FIGURE 13–
Nonzero-level detectors.
zener diode to set the reference voltage ( V
REF
! V
Z
). As long as V
in
is less than V
REF
, the
Trương Công Dung Nghi
25
in
t
2
UTP
LTP
out ( max )
out ( max ) (c) Device triggers only once when UTP or LTP is reached; thus, there is immunity to noise that is riding on the input signal. hen the output is at the maximum positive voltage and the input ceeds UTP, the output switches to the maximum negative voltage. (b) When the output is at the m goes below LTP, the outpu positive voltage. " FIGURE 13– Operation of a comparator with hysteresis. R 1
R 2 V out V in
e feedback t ax ) ax ) only once when UTP or LTP is reached; munity to noise that is riding on the input voltage. R 1
R 2 V in V LTP (b) When the output is at the maximum negative voltage and the input goes below LTP, the output switches back to the maximum positive voltage.
out ( max ) levels are referred to as the upper trigger point (UTP) and the lower his two-level hysteresis is established with a positive feedback n in Figure 13–7. Notice that the noninverting input is connected divider such that a portion of the output voltage is fed back to the l is applied to the inverting (-)input in this case. (+) n of the comparator with hysteresis is illustrated in Figure 13–8. ut voltage is at its positive maximum,! V out ( max ). The voltage fed ng input is V UTP and is expressed as V UTP ! R 2 R 1 " R 2 ( " V out ( max ) )
