Download Basics of Digital Electronics. and more Assignments Digital Electronics in PDF only on Docsity!
ExperimentNo. 1
AIM:Tostudy&designbasicgates.
APPARATUS REQUIRED:IC’s 7 408 , 7404 , 7432 , 7486 ,connecting wire,LED,
Breadboard,powersupply.
THEORY:Circuitthattakesthelogicaldecisionandtheprocessarecalledlogicgates.
Eachgatehasoneormoreinputandonlyoneoutput. ANDGATE:TheANDgateperformsalogicalmultiplicationcommonlyknownasAND functions.Theoutputishighwhenboththeinputsarehigh.Theoutputislow level whenanyoneoftheinputsislow. ORGATE:TheORgateperformsalogicaladditioncommonlyknownasORfunction. Theoutputishighwhenanyoneoftheinputsishigh.Theoutputislowlevelwhenboth theinputsarelow. NOTGATE:TheNOTgateiscalledaninverter.Theoutputishighwhentheinputislow. Theoutputislowwhentheinputishigh. X-ORGATE:Theoutputishighwhenanyoneoftheinputsishigh.Theoutputislow whenboththeinputsarelowandboththeinputsarehigh.
PROCEDURE:
(i)Connectionsaregivenaspercircuitdiagram. (ii)Logicalinputsaregivenaspercircuitdiagram. (iii)Observetheoutputandverifythetruthtable. ANDGATE: Symbol: Truthtable:
Pindiagram: ORGATE: Symbol: Truthtable: Pindiagram NOTGATE: Symbol: Truthtable:
EXPERIMENT
AIM:Torealizeandminimizefive&sixvariableusingK-mapmethod. THEORY:A5-variableK-Mapisdrawnasbelow.Inthisbooleantable,from 0to1 5 ,Ais 0andfrom 16to3 1 ,Ais 1. Givenfunction,Y(A,B,C,D,E)=Σ( 0 , 4 , 8 , 12 , 16 , 18 , 20 , 22 )+d( 24 , 26 , 28 , 30 , 31 ) Since,thebiggestnumberis 30 ,weneedtohave5variablestodefinethisfunction. Let’sdrawK-Mapforthisfunctionbywriting1incellsthatarepresentinfunctionand inrestofthecells.
y=D’.E’+A.E
A6-variableK-Mapisdrawnasbelow: EXAMPLE Given function,F(A,B,C,D,E,F)=Σ( 2 , 3 , 6 , 7 , 14 , 15 , 26 , 27 , 30 , 31 , 40 , 41 , 42 , 43 , 56 , 57 , 62 , 63 )+Σ d ( 1 , 11 , 18 , 19 , 22 , 23 , 44 , 45 , 46 , 47 , 58 , 59 , 60 , 61 ) AnsY=A’E+AC EXAMPLE F(A,B,C,D,E,F)=Σ( 0 , 1 , 2 , 3 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 28 , 29 , 30 , 31 , 42 , 43 , 46 , 47 , 58 , 59 , 62 , 63 )
EXPERIMENT
AIM:ToverifytheoperationofMultiplexerandDe-multiplexer.
APPARATUS:
IC7 400 ,IC7 410 ,IC7 420 ,IC7 404 ,IC7 4153 ,IC7 4155 ,PatchCords&ICTrainerKit.
THEORY:
MULTIPLEXER:
Multiplexersareveryusefulcomponentsindigitalsystems.Theytransferalarge numberof selectionsignals.Multiplexermeansmanytoone.Amultiplexerisacircuitwithmany inputsbutonlyoneoutput.Byusingcontrolsignals(selectlines)wecanselectany inputtotheoutput.Multiplexerisalsocalledasdataselectorbecausetheoutputbit dependsontheinputdatabitthatisselected.Thegeneralmultiplexercircuithas2n inputsignals,ncontrol/selectsignalsand1outputsignal.
LogicalDiagram:
Logicalexpression:OutputY=E’S 1 ’S 0 ’I0+E’S 1 ’S 0 I1+E’S 1 S 0 ’I2+E’S 1 S 0 I 3
RealizationusingNANDGates:
IC7 4150 :
TruthTable:
IC7 4154 :
TruthTable:
PROCEDURE:
Checkallthecomponentsfortheirworking. InserttheappropriateICintotheICbase. Makeconnectionsasshowninthecircuitdiagram. VerifytheTruthTableandobservetheoutputs.
PRECAUTIONS:
1 .)MaketheconnectionsaccordingtotheICpindiagram. 2 .)Theconnectionsshouldbetight. 3 .)TheVccandgroundshouldbeappliedcarefullyatthespecifiedpinonly.
RESULT:
OperationofMultiplexerandDe-Multiplexerhasbeenstudied.
account.Thiscarrybitfrom itspreviousstageiscalledcarry-inbit.Acombinational logiccircuitthataddstwodatabits,AandB,andacarry-inbit,Cin,iscalledafull-adder. TheBooleanfunctionsdescribingthefull-adderare: S=A’B’Cin+AB’Cin’+A’BCin’+ABCin C=AB+AC+BC
TruthTableofHalfadder:
TruthTableofFulladder:
LogicDiagram:
PROCEDURE:
1 .Checkthecomponentsfortheirworking. 2 .InserttheappropriateICintotheICbase. 3 .Makeconnectionsasshowninthecircuitdiagram. 4 .VerifytheTruthTableandobservetheoutputs.
PRECAUTIONS:
Alltheconnectionshouldbetightandproper. HandletheIC’scarefully. Checktheconnectiononceagainbeforeswitchingondigitaltrainerkit.
RESULT:
Thetruthtableoftheabovecircuitsareverified.
EXPERIMENT
AIM:Tostudyhalfsubtractorandfullsubtractor.
APPARATUS:
IC7 408 (ANDgate),IC7 486 (EX-ORgate),IC7 432 (ORgate),PatchCords&ICTrainer Kit.
THEORY:
Logicdiagram:
PROCEDURE:
Checkthecomponentsfortheirworking. InserttheappropriateICintotheICbase. Makeconnectionsasshowninthecircuitdiagram.
VerifytheTruthTableandobservetheoutputs.
PRECAUTIONS:
1 .Alltheconnectionshouldbetightandproper 2 .HandletheIC’scarefully 3 .Checktheconnectiononceagainbeforeswitchingondigitaltrainerkit.
RESULT: Thetruthtableoftheabovecircuitsisverified.
EXPERIMENT
AIM:ToverifythetruthtableofSR,JK,TandDflipflop.
APPARATUS:
IC7 408 ,IC7 404 ,IC7 402 ,IC7 400 ,PatchCords&ICTrainerKit.
THEORY:
Logiccircuitsthatincorporatememorycellsarecalled sequentiallogiccircuits;their outputdependsnotonlyuponthepresentvalueoftheinputbutalsoupontheprevious values.Sequentiallogiccircuitsoftenrequireatiminggenerator(aclock)fortheir operation.Thelatch(flip-flop)isabasicbi-stablememoryelementwidelyusedin sequentiallogiccircuits.Usuallytherearetwooutputs,Qanditscomplementaryvalue. Someofthemostwidelyusedlatchesarelistedbelow.
SRLATCH:
AnS-Rlatchconsistsoftwocross-coupledNORgates.AnS-Rflip-flopcanalsobe designusingcross-coupledNANDgatesasshown. Thetruthtablesofthecircuitsareshownbelow.A clocked S-R flip-flop hasan additionalclockinputsothattheSandRinputsareactiveonlywhentheclockishigh. Whentheclockgoeslow,thestateofflip-flopislatchedandcannotchangeuntilthe clockgoeshighagain.Therefore,theclockedS-Rflip-flopisalsocalled“enabled”S-R flip-flop.ADlatchcombinestheSandRinputsofanS-Rlatchintooneinputbyadding aninverter. Whentheclockishigh,theoutputfollowstheDinput,andwhentheclockgoeslow,the stateislatched. AnS-Rflip-flopcanbeconvertedtoT-flipflopbyconnectingSinputtoQbandRtoQ.
ConversionofSRflipfloptoTflipflop: ConversionofSRtoDFlipFlop:
ConversionofSRtoJKflipflop:
