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Arithmetic Building Blocks

•^

Datapath elements

•^

Adder design^ –^

Static adder

-^

Dynamic adder

•^

Multiplier design^ –^

Array multipliers

•^

Shifters, Parity circuits

A Generic Digital Processor

MEMORY DATAPATH

CONTROL

Input-Output

Bit-Sliced Design

Bit 3Bit 2Bit 1Bit 0

Control

Tile identical processing eleme

nts

Data-in

Data-out

Register

Adder

Shifter

Multiplier

Signals

Data

Control

Metal 2(control) Metal 1(data)

Single-Bit Addition

Half Adder

Full Adder

S

Cout B A

S

Cout C B A

A^

B S Cout

A^

B C S Cout

S^ out

A^

B

C^

=^ ⊕ A B =^ g^

out^

(^ , ,^

)

S^

A^

B^

C

C^

MAJ

A B C =^

⊕^

⊕

The Binary Adder

A^

B

Cout

S um

Cin

Fulladder

Sum = A

⊕^

B^ ⊕

C

= ABC

• ABCi

• ABCi

• ABCi

i

Co^

= AB + BC

• ACi

i

Sum and Carry as a functions

of P, G

Define 3 new variable which ONLY depend on A, B Gen erate (G) = ABProp agate (P) = A

+B

Complimentary Static CMOS Full

Adder

VDD

VDD

VDD

VDD

A^

B Ci

S

Co X

B A Ci

A B

B A

Ci A B^

Ci

A B Ci^ Ci A^ B B A

28 Transistors

Note:1) S = ABC

• Ci

(A + B + Co

)i

2. Placement of C

i

3. Two inverter stages for

each C

o

O(N) delay

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Inversion Property A

B

S

Co

Ci^

FA

A^

B

S

Co

Ci^

FA

Inverting all inputs results in inverted outputs

A better structure: the Mirror

Adder

VDD Ci

A B B A

B A

A^

B

Kill Generate

"0"-Propagate"1"-Propagate

VDD

Ci

A^

B^

Ci

A B Ci Ci A B

B A

VDD

S

Co

24 transistors

The Mirror Adder

• Symmetrical NMOS and PMOS chains
  • identical rising and falling transitions if the NMOS and PMOS devices areproperly sized.– Maximum of two series transistors in the carry-generation circuitry. -^

Critical issue: minimization of the capacitance at C

.o

• Reduction of the diffusion capacitances important.– The capacitance at C

composed of four diffusion capacitances, twoo

internal gate capacitances, and six gate capacitances in the connectingadder cell.

-^

Transistors connected to C

placed closest to output.i

• Only the transistors in carry stage have to be optimized forspeed. All transistors in the sum stage can be minimal size.

VDD

Carry-Bypass Adder

FA^

FA^

FA^

FA

P^0

G^1

P^0

G^1

P^2

G^2

P^3

G^3

Co,

Co,

Co,

Co,

Ci,

FA^

FA^

FA^

FA

P^0

G^1

P^0

G^1

P^2

G^2

P^3

G^3 Co,

Co,

Co,

Ci,

Co, BP=P

Po^1 PP^2

3

Idea: If (P0 and P 1 and P 2 and P3 = 1)then C

o^

= C

, else “kill” or “generate”. 0

Carry-Bypass Adder (cont.)^ S e tu p C arryPropagati on S u m

S e tu p C arryPro pagati on S u m

S e tu p C arryPropagati on S u m

S e tu p C arryPropagati on S u m

Bit 0-

Bit 4-

Bit 8-

Bit 12-

C^ i,

Design N-bit adder using N/M equal length stagese.g. N = 16, M = 4What is the critical path?

t= tp^

setup

+ Mt

carry

+ (N/M-1)t

bypass

+ Mt

carry

+ t

sum

, i.e. O(N)

Carry Ripple versus Carry Bypass

N

tp

ripple adder bypass adder

4..