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Microelectronics Technology: Understanding Junction and Diffusion Capacitance in Diodes - , Assignments of Electrical and Electronics Engineering

Solutions to class activity 16 questions related to the physical origins, values, and differences between junction and diffusion capacitance in p-n diodes. It includes calculations for reverse bias conductance, junction capacitance, and diffusion admittance.

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Pre 2010

Uploaded on 08/09/2009

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ECSE-2210 Microelectronics Technology
Class Activity 16 – Solution
1. What is the physical origin of the junction capacitance (or depletion layer
capacitance)?
The in and out movement of the majority carriers about the steady state depletion
width in response to the applied ac signal gives rise to the junction capacitance.
Effectively, it looks like the plus and the minus charges are alternatively being added
and subtracted from two planes inside the diode with a width W, similar to what
happens in a parallel plate capacitor.
2. What is the physical origin of the diffusion capacitance?
Changes in the stored minority carriers in the quasi-neutral region in response to the
applied ac signal gives rise to the diffusion capacitance. In response to an ac signal,
the minority carrier distributions oscillate about their dc values resulting in an
additional capacitance.
3. Why is the diffusion capacitance negligible under reverse bias?
The concentration of minority carriers stored in reverse-bias is very small. So, any
change will be even smaller.
4. What is the value of the reverse-bias conductance for an ideal diode?
The reverse bias conductance is zero for an ideal diode.
5. Write the equation for the reverse bias conductance for a real p+-n diode if IR-G is
dominating in reverse bias.
IR-G = – q A ni W / 2
τ
o with W = [2
ε
/ q ND × (Vbi VA)]1/2
So, dI / dV = q A ni W / 2
τ
o × [1 / (Vbi VA)]
6. Given a planar p+-n Si step junction diode with an n-side doping of ND = 1015 cm-3 at
T = 300 K, determine the junction capacitance at –1 V reverse bias. Assume that the
Fermi-level is at the valence band edge in the p+-region. Junction area A = 1 cm2. At
zero bias, will the junction capacitance be higher or lower than the one calculated
above? (Hint: Calculate Vbi, then W and then the junction capacitance).
First find Vbi.
Vbi = 0.55 V+ 0.0259 V × ln (1015/1010)
= 0.848 V
W = [2
ε
Si/qND × (VbiVA)]1/2
W = [(2
ε
Si/q) × (1/ND)(0.848 V + 1 V)]1/2
= 1.52 × 10-4 cm.
So, Cj =
ε
Si A/W
= 10-12x 1/1.52 × 10-4
= 6.57 nF.
At zero bias, the junction capacitance will be larger than the above value since the
depletion layer width will be smaller.
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ECSE-2210 Microelectronics Technology Class Activity 16 – Solution

  1. What is the physical origin of the junction capacitance (or depletion layer capacitance)? The in and out movement of the majority carriers about the steady state depletion width in response to the applied ac signal gives rise to the junction capacitance. Effectively, it looks like the plus and the minus charges are alternatively being added and subtracted from two planes inside the diode with a width W , similar to what happens in a parallel plate capacitor.
  2. What is the physical origin of the diffusion capacitance? Changes in the stored minority carriers in the quasi-neutral region in response to the applied ac signal gives rise to the diffusion capacitance. In response to an ac signal, the minority carrier distributions oscillate about their dc values resulting in an additional capacitance.
  3. Why is the diffusion capacitance negligible under reverse bias? The concentration of minority carriers stored in reverse-bias is very small. So, any change will be even smaller.
  4. What is the value of the reverse-bias conductance for an ideal diode? The reverse bias conductance is zero for an ideal diode.
  5. Write the equation for the reverse bias conductance for a real p+-n diode if I R-G is dominating in reverse bias.

I R-G = – q A n i W / 2 τo with W = [2 ε / q N D × ( V bi – V A)]1/

So, d I / d V = q A n i W / 2 τo × [1 / ( V bi – V A)]

  1. Given a planar p+-n Si step junction diode with an n-side doping of N D = 10^15 cm-3^ at T = 300 K, determine the junction capacitance at –1 V reverse bias. Assume that the Fermi-level is at the valence band edge in the p+-region. Junction area A = 1 cm^2. At zero bias, will the junction capacitance be higher or lower than the one calculated above? (Hint: Calculate V bi , then W and then the junction capacitance). First find V bi. V bi = 0.55 V+ 0.0259 V × ln (10 15 /10^10 ) = 0.848 V

W = [2 εSi / qN D × ( V bi – V A)]1/

W = [(2 εSi / q ) × (1/ N D)(0.848 V + 1 V)]1/

= 1.52 × 10-4^ cm.

So, C j = εSi A / W

= 10 -12^ x 1/1.52 × 10 - = 6.57 nF. At zero bias, the junction capacitance will be larger than the above value since the depletion layer width will be smaller.

  1. A particular ideal p +n junction has a reverse saturation current of 1 × 10-14^ A. The hole lifetime in the n-side is 1 × 10-6^ s. What will be the diode diffusion admittance at

a forward bias of 0.6 V? (Write the answer in terms of ω). Draw the small signal

equivalent circuit for the diode. I = I 0 exp ( qV / kT ) I ( V = 0.6 V) = 1.15 × 10 -4^ A

Diffusion conductance: G D = qI / ( kT ) = 1.15 × 10-4^ / 0. = 4.44 × 10-3^ S

Diffusion capacitance: C D = qI τp / ( kT )

= 1.15× 10-4^ × 10 -6^ /0.

= 4.44 nF

Æ Y D = GD + jω CD

= 4.44 × 10 -3^ S + j ω × 4.44 × 10 -9^ F

The small signal equivalent circuit under forward bias is as shown in the figure above.

  1. Consider three p+-n junctions as shown below. Which one will have the highest junction capacitance? Which one will have the lowest junction capacitance? Try to understand the physical reasoning.

Of the three diodes I will have the least depletion region width W and III will have the largest width. As the junction capacitance and the depletion width are inversely proportional to each other, diode III will have the least capacitance and diode I will have the largest capacitance.

p+^ N D=10 15 cm-3^ p +^ N D=10 17 cm- p+ intrinsic

N D=10 15 cm-