Lab Assignment 4
Task# 01
Create a new project in ModelSim, add the files containing 8-bit adder/subtactor
module and Self-testing Stimulus module to the project
Compile and run the simulation of 8-bit adder/subtractor in ModelSim
Self-testing Stimulus should Display Error message if there is any error in the design.
Also show timing waveforms to Lab Instructor
Task# 02
Write Verilog code in behavioral modeling for Mealy Finite State Machine (FSM)
Write Stimulus module to verify FSM design. Stimulus module should give inputs to
design module and display corresponding outputs using $monitor.
Compile and run the simulation in ModelSim and display output waveforms as well
Task# 03
Write Verilog code in behavioral modeling for Moore Finite State Machine (FSM)
Write Stimulus module to verify FSM design. Stimulus module should give inputs to
design module and display corresponding outputs using $monitor.
Compile and run the simulation in ModelSim and display output waveforms as well
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