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Memory Consistency Models - Parallel Computer Architecture - Lecture Slides

Slides, Computer Science

Post: March 28th, 2013
Description
These are the Lecture Slides of Parallel Computer Architecture which includes Conflict Resolution, Cache Miss, Write Serialization, In-Order Response, Multi-Level Caches, Dependence Graph etc.Key important points are: Memory Consistency Models, Sequential Consistency, Relaxed Models, Total Store Ordering, Weak Ordering, Coherence Protocol, Foundation
These are the Lecture Slides of Parallel Computer Architecture which includes Conflict Resolution, Cache Miss, Write Serialization, In-Order Response, Multi-Level Caches, Dependence Graph etc.Key important points are: Memory Consistency Models, Sequential Consistency, Relaxed Models, Total Store Ordering, Weak Ordering, Coherence Protocol, Foundation
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Contents
Objectives_template Module 15: "Memory Consistency Models" Lecture 34: "Sequential Consistency and Relaxed Models" Memory Consistency Models Memory consistency SC SC in MIPS R10000 Relaxed models Total store ordering PC and PSO TSO, PC, PSO Weak ordering (WO) [From Chapters 9 and 11 of Culler, Singh, Gupta] [Additional reading: Adve and Gharachorloo , WRL Tech Report, 1995] file:///E|/parallel_com_arch/lecture34/34_1.htm[6/13/2012 12:15:56 PM] Objectives_template Module 15: "Memory Consistency Models" Lecture 34: "Sequential Consistency and Relaxed Models" Memory consistency Coherence protocol is not enough to completely specify the output(s) of a parallel program Coherence protocol only provides the foundation to reason about legal outcome of accesses to the same memory location Consistency model tells us the possible outcomes arising from legal ordering of accesses to all memory locations A shared memory machine advertises the supported consistency model; it is a “contract” ..

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