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Concurrent Signal - Sequential Logic Design - Lecture Slides

Slides, Digital Logic Design

Post: March 18th, 2013
Description
Its one of the Sequential Logic Design lectures. Its key points are: Concurrent Signal, Decoders Using Structural, Concurrent Logic Behavior, Expression Changes, Left Hand Side, Architecture, Gates Operate, Gate Relative, Actual Value, Cause a Glitch
Its one of the Sequential Logic Design lectures. Its key points are: Concurrent Signal, Decoders Using Structural, Concurrent Logic Behavior, Expression Changes, Left Hand Side, Architecture, Gates Operate, Gate Relative, Actual Value, Cause a Glitch
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Contents
Sequential Logic Design Lecture #10 • Agenda 1. VHDL : Concurrent Signal Assignments 2. Decoders using Structural VHDL • Announcements 1. HW #4 due 2. HW #5 assigned Docsity.com Concurrent Signal Assignments • Concurrency - the way that our designs are simulated is important in modeling real HW behavior - components are executed concurrently (i.e., at the same time) - VHDL gives us another method to describe concurrent logic behavior called "Concurrent Signal Assignments" - we simply list our signal assignments (<=) after the "begin" statement in the architecture - each time any signal on the Right Hand Side (RHS) of the expression changes, the Left Hand Side (LHS) of the assignment is updated. - operators can be included (and, or, +, …) Docsity.com Concurrent Signal Assignments • Concurrent Signal Assignment Example entity TOP is port (A,B,C X end entity TOP; node1 : in : out STD_LOGIC; STD_LOGIC); architecture TOP_arch of TOP is signal begin node1 X <= A xor B; ..

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